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SN74LS293D PDF预览

SN74LS293D

更新时间: 2024-09-08 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 207K
描述
DECADE COUNTER; 4-BIT BINARY COUNTER

SN74LS293D 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.17其他特性:DIVIDE BY 2 AND DIVIDE BY 8 FUNCTIONS
计数方向:UP系列:LS
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):15 pF
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:32000000 Hz最大I(ol):0.008 A
工作模式:ASYNCHRONOUS位数:3
功能数量:2端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5 V
最大电源电流(ICC):15 mA传播延迟(tpd):51 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:16 MHz
Base Number Matches:1

SN74LS293D 数据手册

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SN54/74LS290  
SN54/74LS293  
DECADE COUNTER;  
4-BIT BINARY COUNTER  
The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit ripple type  
counters partitioned into two sections. Each counter has a divide-by-two sec-  
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section  
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each  
section can be used separately or tied together (Q to CP)to form BCD,  
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated  
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set  
(Preset 9).  
DECADE COUNTER;  
4-BIT BINARY COUNTER  
LOW POWER SCHOTTKY  
Corner Power Pin Versions of the LS90 and LS93  
Low Power Consumption . . . Typically 45 mW  
High Count Rates . . . Typically 42 MHz  
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary  
Input Clamp Diodes Limit High Speed Termination Effects  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
NOTE:  
1
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
LS290  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
LS293  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
1.5 U.L.  
2.0 U.L.  
1.0 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
CP  
CP1  
CP1  
MR1, MR2  
MS1, MS2  
Q0  
Clock (Active LOW going edge) Input to ÷2 Section.  
Clock (Active LOW going edge) Input to ÷5 Section (LS290).  
Clock (Active LOW going edge) Input to ÷8 Section (LS293).  
Master Reset (Clear) Inputs  
Master Set (Preset-9, LS290) Inputs  
Output from ÷2 Section (Notes b & c)  
0.05 U.L.  
0.05 U.L.  
0.05 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0
Q1, Q2, Q3  
Outputs from ÷5 & ÷8 Sections (Note b)  
10 U.L.  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.  
c) The Q Outputs are guaranteed to drive the full fan-out plus the CP Input of the device.  
0
1
FAST AND LS TTL DATA  
5-466  

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