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SN74LS293JS PDF预览

SN74LS293JS

更新时间: 2024-11-02 12:58:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
7页 207K
描述
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14, CERAMIC, DIP-14

SN74LS293JS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.31
Is Samacsys:N其他特性:DIVIDE BY 2 AND DIVIDE BY 8 FUNCTIONS
计数方向:UP系列:LS
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:19.495 mm负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER工作模式:ASYNCHRONOUS
位数:3功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):70 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Counters
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:7.62 mm最小 fmax:42 MHz
Base Number Matches:1

SN74LS293JS 数据手册

 浏览型号SN74LS293JS的Datasheet PDF文件第2页浏览型号SN74LS293JS的Datasheet PDF文件第3页浏览型号SN74LS293JS的Datasheet PDF文件第4页浏览型号SN74LS293JS的Datasheet PDF文件第5页浏览型号SN74LS293JS的Datasheet PDF文件第6页浏览型号SN74LS293JS的Datasheet PDF文件第7页 
SN54/74LS290  
SN54/74LS293  
DECADE COUNTER;  
4-BIT BINARY COUNTER  
The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit ripple type  
counters partitioned into two sections. Each counter has a divide-by-two sec-  
tion and either a divide-by-five (LS290) or divide-by-eight (LS293) section  
which are triggered by a HIGH-to-LOW transition on the clock inputs. Each  
section can be used separately or tied together (Q to CP)to form BCD,  
Bi-quinary, or Modulo-16 counters. Both of the counters have a 2-input gated  
Master Reset (Clear), and the LS290 also has a 2-input gated Master Set  
(Preset 9).  
DECADE COUNTER;  
4-BIT BINARY COUNTER  
LOW POWER SCHOTTKY  
Corner Power Pin Versions of the LS90 and LS93  
Low Power Consumption . . . Typically 45 mW  
High Count Rates . . . Typically 42 MHz  
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary  
Input Clamp Diodes Limit High Speed Termination Effects  
J SUFFIX  
CERAMIC  
CASE 632-08  
14  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
N SUFFIX  
PLASTIC  
CASE 646-06  
14  
NOTE:  
1
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
LS290  
D SUFFIX  
SOIC  
CASE 751A-02  
14  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
LS293  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
1.5 U.L.  
2.0 U.L.  
1.0 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
CP  
CP1  
CP1  
MR1, MR2  
MS1, MS2  
Q0  
Clock (Active LOW going edge) Input to ÷2 Section.  
Clock (Active LOW going edge) Input to ÷5 Section (LS290).  
Clock (Active LOW going edge) Input to ÷8 Section (LS293).  
Master Reset (Clear) Inputs  
Master Set (Preset-9, LS290) Inputs  
Output from ÷2 Section (Notes b & c)  
0.05 U.L.  
0.05 U.L.  
0.05 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0
Q1, Q2, Q3  
Outputs from ÷5 & ÷8 Sections (Note b)  
10 U.L.  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.  
c) The Q Outputs are guaranteed to drive the full fan-out plus the CP Input of the device.  
0
1
FAST AND LS TTL DATA  
5-466  

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