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SN74HC165DBRE4 PDF预览

SN74HC165DBRE4

更新时间: 2024-10-31 23:03:11
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
19页 576K
描述
8-BIT PARALLEL-LOAD SHIFT REGISTERS

SN74HC165DBRE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SSOP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.09Is Samacsys:N
其他特性:SISO OPERATION ALSO AVAILABLE计数方向:RIGHT
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:6.2 mm
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:25000000 Hz
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:Shift Registers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.3 mm最小 fmax:29 MHz
Base Number Matches:1

SN74HC165DBRE4 数据手册

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ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ ꢀꢁꢉ ꢃꢄ ꢅꢆ ꢇꢂ  
ꢋꢌꢍ ꢎ ꢏꢐꢑꢐ ꢒꢒ ꢓꢒ ꢋꢒ ꢔ ꢐꢕ ꢀꢄꢍ ꢖ ꢎ ꢑꢓꢗ ꢍ ꢀ ꢎꢓ ꢑꢀ  
SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003  
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
D
D
Low Input Current of 1 µA Max  
Complementary Outputs  
Low Power Consumption, 80-µA Max I  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
CC  
Typical t = 13 ns  
pd  
4-mA Output Drive at 5 V  
Parallel-to-Serial Data Conversion  
SN54HC165 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC165 . . . J OR W PACKAGE  
SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SH/LD  
CLK  
E
V
CC  
CLK INH  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
D
C
B
A
3
2
1
20 19  
18  
E
F
D
4
5
6
7
8
F
G
H
C
17  
16  
15  
14  
NC  
G
NC  
B
Q
SER  
H
H
A
GND  
Q
H
9 10 11 12 13  
NC − No internal connection  
description/ordering information  
The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q )  
H
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled  
by a low level at the shift/load (SH/LD) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function  
and a complementary serial (Q ) output.  
H
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC165N  
SN74HC165N  
SN74HC165D  
SN74HC165DR  
SN74HC165DT  
SN74HC165NSR  
SN74HC165DBR  
SN74HC165PW  
SN74HC165PWR  
SN74HC165PWT  
SNJ54HC165J  
HC165  
SOP − NS  
HC165  
HC165  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC165  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC165J  
SNJ54HC165W  
SNJ54HC165FK  
SNJ54HC165W  
SNJ54HC165FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢔ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢍ ꢒꢋ ꢏꢑ ꢖ ꢋꢰꢊꢂ ꢰꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢔ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
ꢥ ꢝ ꢜꢢꢤ ꢡꢡꢙ ꢚꢮ ꢨ ꢜꢤꢡ ꢚ ꢜꢠ ꢚ ꢤꢢꢤꢡ ꢡꢟꢝ ꢙ ꢧꢭ ꢙ ꢚꢢꢧ ꢣ ꢨꢤ ꢠꢤꢡ ꢠꢙꢚ ꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢩ  
ꢏꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢎꢤꢫ ꢟꢡ ꢍꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ  
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢏꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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