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SN74HC165DBRG4 PDF预览

SN74HC165DBRG4

更新时间： 2024-11-23 15:52:15
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
26页 1205K
描述
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, GREEN, PLASTIC, SSOP-16

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SN74HC165DBRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SSOP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.09Is Samacsys：N
其他特性：SISO OPERATION ALSO AVAILABLE计数方向：RIGHT
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：6.2 mm
逻辑集成电路类型：PARALLEL IN SERIAL OUT最大频率@ Nom-Sup：25000000 Hz
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：190 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：29 MHz
Base Number Matches：1

SN74HC165DBRG4 数据手册

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SN54HC165, SN74HC165  
www.ti.com  
SCLS116G –DECEMBER 1982–REVISED AUGUST 2013  
8-BIT PARALLEL-LOAD SHIFT REGISTERS  
Check for Samples: SN54HC165, SN74HC165  
1
FEATURES  
DESCRIPTION  
The ’HC165 devices are 8-bit parallel-load shift  
•
•
•
•
•
•
•
•
•
•
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-μA Max ICC  
Typical tpd = 13 ns  
registers that, when clocked, shift the data toward a  
serial (QH) output. Parallel-in access to each stage is  
provided by eight individual direct data (A−H) inputs  
that are enabled by a low level at the shift/load  
(SH/LD) input. The ’HC165 devices also feature a  
clock-inhibit (CLK INH) function and a complementary  
serial (QH) output.  
±4-mA Output Drive at 5 V  
Low Input Current of 1 μA Max  
Complementary Outputs  
Clocking is accomplished by a low-to-high transition  
of the clock (CLK) input while SH/LD is held high and  
CLK INH is held low. The functions of CLK and CLK  
INH are interchangeable. Since a low CLK and a low-  
to-high transition of CLK INH also accomplish  
clocking, CLK INH should be changed to the high  
level only while CLK is high. Parallel loading is  
inhibited when SH/LD is held high. While SH/LD is  
low, the parallel inputs to the register are enabled  
independently of the levels of the CLK, CLK INH, or  
serial (SER) inputs.  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
Parallel-to-Serial Data Conversion  
SN54HC165 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC165 . . . J or W PACKAGE  
SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SH/LD  
CLK  
E
VCC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CLK INH  
D
3
2
1
20 19  
18  
E
F
D
4
5
6
7
8
F
C
C
17  
16  
15  
14  
G
B
NC  
G
NC  
B
H
A
QH  
GND  
SER  
QH  
H
A
9 10 11 12 13  
NC − No internal connection  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1982–2013, Texas Instruments Incorporated  
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