ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢆ
ꢃ ꢉꢋꢌ ꢍ ꢀꢎ ꢁꢅꢄꢏꢐ ꢁꢐ ꢑꢀ ꢋꢌ ꢁꢒꢏꢎ ꢅꢐ ꢑ ꢁꢍ ꢓꢏ
SCLS584A − MAY 2004 − REVISED APRIL 2008
D
D
D
D
D
D
D
D
Qualified for Automotive Applications
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
Carry Output for n-Bit Cascading
Synchronous Counting
D
D
Synchronously Programmable
Low Power Consumption, 80-µA Max I
CC
PW PACKAGE
(TOP VIEW)
Typical t = 14 ns
pd
4-mA Output Drive at 5 V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
V
CC
RCO
Low Input Current of 1 µA Max
Internal Look-Ahead for Fast Counting
Q
Q
Q
Q
A
B
C
D
B
C
D
description/ordering information
This synchronous, presettable counter features an
internal carry look-ahead for application in
high-speed counting designs. The SN74HC163 is a
4-bit binary counter. Synchronous operation is
provided by having all flip-flops clocked
ENP
GND
ENT
LOAD
simultaneously so that the outputs change coincident with each other when instructed by the count-enable
(ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally
associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on
the rising (positive-going) edge of the clock waveform.
This counter is fully programmable; that is, it can be preset to any number between 0 and 9 or 15. As presetting
is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the SN74HC163 is synchronous. A low level at the clear (CLR) input sets all four of the
flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
{
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
A
PACKAGE
−40°C to 85°C
TSSOP − PW Tape and reel
SN74HC163IPWRQ1
HC163I
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢔ
ꢔ
ꢏ
ꢐ
ꢥ
ꢕ
ꢠ
ꢑ
ꢅ
ꢞ
ꢍ
ꢟ
ꢌ
ꢙ
ꢐ
ꢗ
ꢁ
ꢘ
ꢕ
ꢒ
ꢍ
ꢒ
ꢖ
ꢗ
ꢡ
ꢘ
ꢙ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢝ
ꢝ
ꢖ
ꢖ
ꢙ
ꢙ
ꢗ
ꢗ
ꢖ
ꢞ
ꢞ
ꢢ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢙ
ꢘ
ꢢ
ꢍꢡ
ꢠ
ꢣ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢝ
ꢝ
ꢡ
ꢞ
ꢦ
Copyright 2008 Texas Instruments Incorporated
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢨ
ꢜ
ꢌ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢩ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
ꢚ
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢔ
ꢚ
ꢙ
ꢥ
ꢠ
ꢟ
ꢝ
ꢖ
ꢙ
ꢗ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5秒后页面跳转
SL74HC10N：高性能三输入与非门解析
AIC1781A 电池充电控制器深度解析
Pickering新高压舌簧继电器亮相汽车测试博览会
采用MCU+MPU双处理器架构实现的创新应用设计探索
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
