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SN74F112

更新时间： 2024-11-29 22:53:35
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德州仪器 - TI 触发器
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5页 75K
描述
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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SN74F112 数据手册

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SN74F112  
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP  
WITH CLEAR AND PRESET  
SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993  
D OR N PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
V
1CLK  
1K  
1
2
3
4
5
6
7
8
16  
CC  
description  
15 1CLR  
14 2CLR  
1J  
The SN74F112 contains two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), dataattheJandKinputsmeetingthesetup  
time requirements is transferred to the outputs on  
the negative-going edge of the clock pulse. Clock  
triggering occurs at a voltage level and is not  
directly related to the rise time of the clock pulse.  
Following the hold-time interval, data at the J and  
K inputs may be changed without affecting the  
levels at the outputs. The SN74F112 can perform  
as a toggle flip-flop by tying J and K high.  
13  
12  
11  
10  
9
2CLK  
2K  
1PRE  
1Q  
2J  
1Q  
2PRE  
2Q  
2Q  
GND  
The SN74F112 is characterized for operation from  
0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
L
L
X
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle  
H
H
H
Q
Q
0
0
†
The output levels in this configuration are not guaranteed to  
meet the minimum levels for V . Furthermore, this  
OH  
configuration is nonstable; that is, it will not persist when  
either PRE or CLR returns to its inactive (high) level.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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SN74F112DG4 TI

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SN74F112DR TI

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 		具有清零和预置端的双路负边沿触发式 J-K 触发器 | D | 16 | 0 to 70
SN74F112DRE4 TI

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 		Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-SOIC 0 to 70
SN74F112DRG4 TI

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 		Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-SOIC 0 to 70
SN74F112N TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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