SN74F109DR

更新时间： 2024-11-29 04:51:11

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
6页	98K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SN74F109DR 数据手册

SN54F109, SN74F109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SDFS047A – MARCH 1987 – REVISED OCTOBER 1993

SN54F109 . . . J PACKAGE

SN74F109 . . . D OR N PACKAGE

(TOP VIEW)

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

1CLR

VCC

2CLR

description

These devices contain two independent J-K

positive-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs regardless of the levels of the

other inputs. When PRE and CLR are inactive

(high), data at the J and K input meeting the

setup-time requirements are transferred to the

outputs on the positive-going edge of the clock

pulse. Clock triggering occurs at a voltage level

and is not directly related to the rise time of the

clock pulse. Following the hold time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by

grounding K and trying J high. They also can

perform as D-type flip-flops if J and K are tied

together.

1CLK

1PRE

2CLK

11 2PRE

GND

SN54F109 . . . FK PACKAGE

(TOP VIEW)

20 19

1CLK

1PRE

2CLK

2PRE

9 10 11 12 13

The SN54F109 is characterized for operation over

the full military temperature range of –55°C to

125°C. The SN74F109 is characterized for

operation from 0°C to 70°C.

NC – No internal connection

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK

†

↑

Toggle

↑

†

The output levels are not guaranteed to meet the minimum

levelsforV .Furthermore,thisconfigurationisnonstable;

that is, it will not persist when PRE or CLR returns to its

inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

中文翻译

下载PDF

SN74F109DR 替代型号

型号	品牌	替代类型	描述	数据表
SN74F109DRG4	TI	类似代替	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74F109N	TI	类似代替	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74F109D	TI	类似代替	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74F109DR相关器件

型号	品牌	获取价格	描述	数据表
SN74F109DRE4	TI	获取价格	Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
SN74F109DRG4	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74F109N	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74F109N-10	TI	获取价格	F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
SN74F109N3	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,F-TTL,DIP,16PIN,PLASTIC
SN74F109N3	ROCHESTER	获取价格	J-Kbar Flip-Flop
SN74F10D	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATES
SN74F10D3	TI	获取价格	IC,LOGIC GATE,3 3-INPUT NAND,F-TTL,SOP,14PIN,PLASTIC
SN74F10DE4	ROCHESTER	获取价格	NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDSO14, GREEN, PLASTIC, SOIC-14
SN74F10DE4	TI	获取价格	Triple 3-input positive-NAND gates 14-SOIC 0 to 70

与SN74F109DR相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

52
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

41
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

69
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

65

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74F109DR

SN74F109DR 数据手册

SN74F109DR 替代型号

与SN74F109DR相关器件

与SN74F109DR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74F109DR

SN74F109DR 数据手册

SN74F109DR 替代型号

与SN74F109DR相关器件

与SN74F109DR相关文章

您还可以找

您在本页遇到什么问题？