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SN74F10NE4 PDF预览

SN74F10NE4

更新时间: 2024-11-09 15:52:11
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路
页数 文件大小 规格书
16页 774K
描述
NAND Gate, F/FAST Series, 3-Func, 3-Input, TTL, PDIP14, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-14

SN74F10NE4 技术参数

生命周期:Contact Manufacturer包装说明:0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65系列:F/FAST
JESD-30 代码:R-PDIP-T14长度:19.305 mm
逻辑集成电路类型:NAND GATE功能数量:3
输入次数:3端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):5.3 ns座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN74F10NE4 数据手册

 浏览型号SN74F10NE4的Datasheet PDF文件第2页浏览型号SN74F10NE4的Datasheet PDF文件第3页浏览型号SN74F10NE4的Datasheet PDF文件第4页浏览型号SN74F10NE4的Datasheet PDF文件第5页浏览型号SN74F10NE4的Datasheet PDF文件第6页浏览型号SN74F10NE4的Datasheet PDF文件第7页 
SN54F10, SN74F10  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SDFS039A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F10 . . . J PACKAGE  
SN74F10 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3C  
3B  
3A  
3Y  
description  
These devices contain three independent 3-input  
NAND gates. They perform the Boolean functions  
Y = A B C or Y = A + B + C in positive logic.  
2Y  
GND  
8
The SN54F10 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F10 is characterized for  
operation from 0°C to 70°C.  
SN54F10 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
INPUTS  
OUTPUT  
Y
2A  
NC  
2B  
1Y  
NC  
3C  
NC  
3B  
4
5
6
7
8
A
H
L
B
H
X
L
C
H
X
X
L
17  
16  
15  
14  
L
H
H
H
NC  
2C  
X
X
9 10 11 12 13  
X
logic symbol  
NC – No internal connection  
1
1A  
&
2
12  
6
logic diagram, each gate (positive logic)  
1B  
1Y  
2Y  
3Y  
13  
1C  
3
A
2A  
4
Y
B
C
2B  
5
2C  
9
3A  
10  
8
3B  
11  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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