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SN74CBTLV3126PWG4 PDF预览

SN74CBTLV3126PWG4

更新时间: 2024-11-06 06:12:55
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18页 685K
描述
LOW-VOLTAGE QUADRUPLE FET BUS SWITCH

SN74CBTLV3126PWG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.35
其他特性:BUS SWITCH系列:CBTLV/3B
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
传播延迟(tpd):0.25 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

SN74CBTLV3126PWG4 数据手册

 浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第2页浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第3页浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第4页浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第5页浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第6页浏览型号SN74CBTLV3126PWG4的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ  
SCDS038I − DECEMBER 1997 − REVISED OCTOBER 2003  
D
D
D
Standard ’126-Type Pinout  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
5-Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
Latch-up Performance Exceeds 100 mA per  
JESD 78, Class II  
D, DGV, OR PW PACKAGE  
DBQ PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1B  
2OE  
2A  
2B  
V
CC  
4OE  
V
NC  
1OE  
1A  
1B  
2OE  
2A  
1
2
3
4
5
6
7
8
16  
CC  
15 4OE  
14 4A  
1
14  
4A  
4B  
3OE  
3A  
3B  
1A  
1B  
13 4OE  
12 4A  
2
3
4
5
6
13 4B  
12 3OE  
11  
10  
9
2OE  
2A  
4B  
11  
10  
9
3A  
3B  
NC  
3OE  
3A  
8
GND  
2B  
GND  
2B  
7
8
NC − No internal connection  
description/ordering information  
The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled  
when the associated output-enable (OE) input is low.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
SN74CBTLV3126RGYR  
SN74CBTLV3126D  
CL126  
Tube  
CBTLV3126  
Tape and reel  
SN74CBTLV3126DR  
SN74CBTLV3126DBQR  
SN74CBTLV3126PWR  
SN74CBTLV3126DGVR  
−40°C to 85°C  
SSOP (QSOP) − DBQ Tape and reel  
CL126  
CL126  
CL126  
TSSOP − PW  
TVSOP − DGV  
Tape and reel  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each bus switch)  
INPUT  
FUNCTION  
OE  
L
Disconnect  
H
A port = B port  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢦ  
Copyright 2003, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74CBTLV3126PWG4 替代型号

型号 品牌 替代类型 描述 数据表
74CBTLV3126RGYRG4 TI

完全替代

LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SN74CBTLV3126DR TI

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LOW-VOLTAGE QUADRUPLE FET BUS SWITCH
SN74CBTLV3126PWR TI

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LOW-VOLTAGE QUADRUPLE FET BUS SWITCH

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