ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢃꢋ ꢌ
ꢇ ꢍꢎꢏꢈꢍ ꢇꢆꢌꢐ ꢑ ꢍ ꢄꢆꢌꢇ ꢒ ꢑꢆ ꢅꢓꢀ ꢀ ꢎꢔ ꢆꢄ ꢕ
SCDS034L − JULY 1997 − REVISED OCTOBER 2003
D
D
D
D
Standard ’245-Type Pinout
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
5-Ω Switch Connection Between Two Ports
Rail-to-Rail Switching on Data I/O Ports
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
I
Supports Partial-Power-Down Mode
off
Operation
DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
A1
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
20
A2
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
OE
B1
B2
B3
B4
B5
B6
B7
A3
A4
A5
A6
A7
A8
GND
10
11
NC − No internal connection
NC − No internal connection
description/ordering information
The SN74CBTLV3245A provides eight bits of high-speed bus switching in a standard ’245 device pinout. The
low on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on,
and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists
between the two ports.
This device is fully specified for partial-power-down applications using I . The I feature ensures that
off
off
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − DW
Tape and reel
SN74CBTLV3245ARGYR
SN74CBTLV3245ADW
SN74CBTLV3245ADWR
SN74CBTLV3245ADBQR
SN74CBTLV3245APWR
SN74CBTLV3245ADGVR
CL245A
Tube
CBTLV3245A
Tape and reel
Tape and reel
Tape and reel
Tape and reel
−40°C to 85°C
SSOP (QSOP) − DBQ
TSSOP − PW
CBTLV3245A
CL245A
TVSOP − DGV
CL245A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢖ
ꢖ
ꢗ
ꢍ
ꢨ
ꢘ
ꢣ
ꢓ
ꢄ
ꢡ
ꢆ
ꢢ
ꢔ
ꢜ
ꢍ
ꢚ
ꢁ
ꢛ
ꢘ
ꢌ
ꢆ
ꢌ
ꢙ
ꢚ
ꢤ
ꢛ
ꢜ
ꢢ
ꢝ
ꢞ
ꢟ
ꢟ
ꢠ
ꢠ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢡ
ꢡ
ꢥ
ꢢ
ꢣ
ꢝ
ꢝ
ꢤ
ꢤ
ꢚ
ꢠ
ꢟ
ꢞ
ꢡ
ꢡ
ꢜ
ꢛ
ꢥ
ꢆꢤ
ꢣ
ꢦ
ꢡ
ꢧ
ꢙ
ꢢ
ꢟ
ꢡ
ꢠ
ꢙ
ꢠ
ꢜ
ꢝ
ꢚ
ꢣ
ꢨ
ꢟ
ꢚ
ꢠ
ꢠ
ꢤ
ꢡ
ꢩ
Copyright 2003, Texas Instruments Incorporated
ꢝ
ꢜ
ꢢ
ꢠ
ꢜ
ꢝ
ꢞ
ꢠ
ꢜ
ꢡ
ꢥ
ꢙ
ꢛ
ꢙ
ꢢ
ꢤ
ꢝ
ꢠ
ꢪ
ꢠ
ꢤ
ꢝ
ꢜ
ꢛ
ꢫ
ꢟ
ꢔ
ꢚ
ꢞ
ꢤ
ꢡ
ꢠ
ꢟ
ꢚ
ꢨ
ꢟ
ꢝ
ꢨ
ꢬ
ꢟ
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
ꢝ
ꢝ
ꢟ
ꢚ
ꢠ
ꢭ
ꢩ
ꢖ
ꢝ
ꢜ
ꢨ
ꢣ
ꢢ
ꢠ
ꢙ
ꢜ
ꢚ
ꢥ
ꢝ
ꢜ
ꢢ
ꢤ
ꢡ
ꢡ
ꢙ
ꢚ
ꢮ
ꢨ
ꢜ
ꢤ
ꢡ
ꢚ
ꢜ
ꢠ
ꢚ
ꢤ
ꢢ
ꢤ
ꢡ
ꢡ
ꢟ
ꢝ
ꢙ
ꢧ
ꢭ
ꢙ
ꢚ
ꢢ
ꢧ
ꢣ
ꢨ
ꢤ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265