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SN74AVCH245DGVR PDF预览

SN74AVCH245DGVR

更新时间： 2024-11-23 21:14:43
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
11页 177K
描述
AVC SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, PLASTIC, TVSOP-20

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SN74AVCH245DGVR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP, TSSOP20,.25,16
针数：20Reach Compliance Code：not_compliant
风险等级：5.92其他特性：WITH DIRECTION CONTROL
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：AVCJESD-30 代码：R-PDSO-G20
长度：5 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.4 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：4.4 mm
Base Number Matches：1

SN74AVCH245DGVR 数据手册

 浏览型号SN74AVCH245DGVR的Datasheet PDF文件第2页浏览型号SN74AVCH245DGVR的Datasheet PDF文件第3页浏览型号SN74AVCH245DGVR的Datasheet PDF文件第4页浏览型号SN74AVCH245DGVR的Datasheet PDF文件第5页浏览型号SN74AVCH245DGVR的Datasheet PDF文件第6页浏览型号SN74AVCH245DGVR的Datasheet PDF文件第7页 
SN74AVCH245  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000  
D
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
D
D
D
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Less Than 2-ns Maximum Propagation  
Delay at 2.5-V and 3.3-V V  
CC  
D
Package Options Include Plastic  
Small-Outline (DW), Thin Very  
Small-Outline (DGV), and Thin Shrink  
Small-Outline (PW) Packages  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I and I of  
OH  
OL  
±24 mA at 2.5-V V  
CC  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This octal bus transceiver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to 3.6-V  
CC  
V
operation.  
CC  
The SN74AVCH245 is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
effectively isolated.  
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the  
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.  
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3–33  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN74AVCH245PW TI

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SN74AVCH245PWLE TI

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 		24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outpu
SN74AVCH24T245GRG TI

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 		24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outpu
SN74AVCH24T245GRG/ZRG TI

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 		24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outpu
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SN74AVCH24T245NMU TI

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 		24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outpu

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