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SN74AVCH2T45 PDF预览

SN74AVCH2T45

更新时间: 2024-11-06 03:40:39
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德州仪器 - TI 总线收发器输出元件
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描述
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN74AVCH2T45 数据手册

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SN74AVCH2T45  
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER  
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS  
www.ti.com  
SCES582DJULY 2004REVISED AUGUST 2005  
FEATURES  
Max Data Rates  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
– 500 Mbps (1.8-V to 3.3-V Translation)  
– 320 Mbps (<1.8-V to 3.3-V Translation)  
– 320 Mbps (Translate to 2.5 V or 1.8 V)  
– 180 Mbps (Translate to 1.5 V)  
– 240 Mbps (Translate to 1.2 V)  
Control Inputs VIH/VIL Levels Are Referenced  
to VCCA Voltage  
Fully Configurable Dual-Rail Design Allows  
Each Port to Operate Over the Full 1.2-V to  
3.6-V Power-Supply Range  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
I/Os Are 4.6-V Tolerant  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Ioff Supports Partial-Power-Down Mode  
Operation  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
– 1000-V Charged-Device Model (C101)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
DCT OR DCU PACKAGE  
(TOP VIEW)  
4
3
2
1
5
6
7
8
GND  
A2  
DIR  
B2  
V
V
CCB  
1
2
3
4
8
7
6
5
CCA  
A1  
A2  
B1  
B2  
DIR  
A1  
B1  
V
CCA  
V
CCB  
GND  
DESCRIPTION/ORDERING INFORMATION  
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The  
SN74AVCH2T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as  
low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B  
port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal  
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.  
The SN74AVCH2T45 is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74AVCH2T45YEPR(3)  
Tape and reel  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AVCH2T45YZPR(3)  
–40°C to 85°C  
SSOP – DCT  
Tape and reel SN74AVCH2T45DCTR  
Tape and reel SN74AVCH2T45DCUR  
ET2_ _ _  
ET2_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).  
(3) Package preview  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74AVCH2T45 替代型号

型号 品牌 替代类型 描述 数据表
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