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SN74AVCH24T245NMU PDF预览

SN74AVCH24T245NMU

更新时间: 2024-11-24 02:49:39
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德州仪器 - TI /
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描述
24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outputs

SN74AVCH24T245NMU 数据手册

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SN74AVCH24T245  
SCES588C – AUGUST 2004 – REVISED AUGUST 2020  
24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-  
State Outputs  
transmits data from the A bus to the B bus or from the  
B bus to the A bus, depending on the logic level at the  
1 Features  
Control Inputs VIH/VIL Levels Are Referenced to  
VCCA Voltage  
direction-control (DIR) input. The output-enable ( OE)  
input can be used to disable the outputs so the buses  
are effectively isolated.  
VCC Isolation Feature – If Either VCC Input Is at  
GND, All Outputs Are in the High-Impedance State  
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-  
Voltage-Mode Data Communications  
Fully Configurable Dual-Rail Design Allows Each  
Port to Operate Over Full 1.2-V to 3.6-V Power-  
Supply Range  
Ioff Supports Partial-Power-Down Mode Operation  
I/Os Are 4.6-V Tolerant  
Bus Hold on Data Inputs, Eliminating the Need for  
External Pullups/Pulldowns  
The SN74AVCH24T245 is designed so that the  
control pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1  
OE, 2 OE, 3 OE, 4 OE, 5 OE, and 6 OE) are supplied  
by VCCA  
.
This device is fully specified for partial-power-down  
applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow  
through the device when it is powered down.  
The VCC isolation feature ensures that if either VCC  
input is at GND, then both ports are in the high-  
impedance state.  
Max Data Rates  
– 380 Mbps (1.8-V to 3.3-V Translation)  
– 200 Mbps (<1.8-V to 3.3-V Translation)  
– 200 Mbps (Translate to 2.5 V or 1.8 V)  
– 150 Mbps (Translate to 1.5 V)  
– 100 Mbps (Translate to 1.2 V)  
Latch-Up Performance Exceeds 100 mA Per JESD  
78, Class II  
ESD Protection Exceeds JESD 22  
– 8000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Active bus-hold circuitry holds unused or undriven  
inputs at a valid logic state.  
To ensure the high-impedance state during power up  
or power down, OE should be tied to VCCA through a  
pullup resistor; the minimum value of the resistor is  
determined by the current-sinking capability of the  
driver.  
Device Information  
PART NUMBER  
PACKAGE(1)  
BODY SIZE (NOM)  
SN74AVCH24T245GRG/Z  
RG  
10.00 mm × 4.50  
mm  
LFBGA  
2 Applications  
10.00 mm × 4.50  
mm  
SN74AVCH24T245NMU nFBGA  
Personal Electronics  
Industrial  
Enterprise  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Telecom  
P5  
P6  
2DIR  
1DIR  
A6  
A5  
1OE  
2OE  
3 Description  
D6  
B6  
1A1  
2A1  
D1  
B1  
1B1  
2B1  
This 24-bit noninverting bus transceiver uses two  
separate configurable power-supply rails. The  
SN74AVCH24T245 is optimized to operate with  
VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with  
VCCA/VCCB as low as 1.2 V. The A port is designed to  
track VCCA. VCCA accepts any supply voltage from 1.2  
V to 3.6 V. The B port is designed to track VCCB. VCCB  
accepts any supply voltage from 1.2 V to 3.6 V. This  
allows for universal low-voltage bidirectional  
To Three Other Channels  
To Three Other Channels  
To Three Other Channels  
To Three Other Channels  
To Three Other Channels  
To Three Other Channels  
P3  
P4  
4DIR  
3DIR  
A4  
A3  
3OE  
4OE  
H6  
F6  
3A1  
4A1  
H1  
F1  
4B1  
3B1  
P1  
P2  
6DIR  
5DIR  
A2  
A1  
5OE  
6OE  
M6  
K6  
6A1  
5A1  
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-  
V, and 3.3-V voltage nodes.  
M1  
K1  
6B1  
5B1  
The SN74AVCH24T245 is designed for asynchronous  
communication between data buses. The device  
Figure 3-1. Logic Diagram  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 

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