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SN74AUC1G04YEAR PDF预览

SN74AUC1G04YEAR

更新时间: 2024-11-19 22:06:35
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 309K
描述
SINGLE INVERTER GATE

SN74AUC1G04YEAR 数据手册

 浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第2页浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第3页浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第4页浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第5页浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第6页浏览型号SN74AUC1G04YEAR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢃ  
ꢀꢊ ꢁꢈ ꢋ ꢌ ꢊꢁ ꢍꢌꢎ ꢏꢌ ꢎ ꢈ ꢄꢏꢌ  
SCES370L − SEPTEMBER 2001 − REVISED NOVEMBER 2003  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
2
3
5
4
NC  
A
GND  
V
Y
CC  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
NC − No internal connection  
D
D
D
D
D
Sub 1-V Operable  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Max t of 2.2 ns at 1.8 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
3 4  
2
GND  
A
DNU  
Y
V
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1 5  
CC  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
DNU − Do not use  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This single inverter gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V  
CC  
V
operation.  
CC  
The SN74AUC1G04 performs the Boolean function Y = A.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74AUC1G04YEAR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
SN74AUC1G04YZAR  
SN74AUC1G04YEPR  
SN74AUC1G04YZPR  
Tape and reel  
_ _ _UC_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SOT (SOT-23) − DBV  
SOT (SC-70) − DCK  
Tape and reel  
Tape and reel  
SN74AUC1G04DBVR  
SN74AUC1G04DCKR  
U04_  
UC_  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢏꢞ  
Copyright 2003, Texas Instruments Incorporated  
ꢚ ꢞ ꢛ ꢚꢓ ꢔꢨ ꢖꢕ ꢙ ꢡꢡ ꢟꢙ ꢗ ꢙ ꢘ ꢞ ꢚ ꢞ ꢗ ꢛ ꢣ  
ꢛꢓ  
ꢙꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AUC1G04YEAR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G04YEPR TI

完全替代

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完全替代

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SN74AUC1G04YZPR TI

完全替代

SINGLE INVERTER GATE

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