SN54ALVTH16841, SN74ALVTH16841
2.5-V/3.3-V 20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES077B – JULY 1996 – REVISED JULY 1997
SN54ALVTH16841 . . . WD PACKAGE
SN74ALVTH16841 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
High-Impedance State During Power Up
and Power Down
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
5-V I/O Compatible
High-Drive Capability (–32 mA/64 mA)
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
V
V
CC
CC
1Q5
1D5
Exceeds V
CC
1Q6
1D6
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
1Q7 10
47 1D7
GND
1Q8
GND
1D8
11
12
46
45
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
1Q9 13
1Q10 14
2Q1 15
2Q2 16
44 1D9
43 1D10
42 2D1
41 2D2
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
2Q3
17
40
2D3
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
GND 18
2Q4 19
2Q5 20
2Q6 21
39 GND
38 2D4
37 2D5
36 2D6
description
V
22
35
V
CC
CC
The ’ALVTH16841 are 20-bit bus-interface D-type
latches with 3-state outputs designed for 2.5-V or
2Q7 23
2Q8 24
GND 25
2Q9 26
2Q10 27
2OE 28
34 2D7
33 2D8
32 GND
31 2D9
30 2D10
29 2LE
3.3-V V
operation, but with the capability to
CC
provide a TTL interface to a 5-V system
environment.
The ’ALVTH16841 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, unidirectional bus drivers, and working
registers.
The ’ALVTH16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type
latches. Thedevicehasnoninvertingdata(D)inputsandprovidestruedataatitsoutputs. Whilethelatch-enable
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE is taken
low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable (OE) input does not affect the internal operation of the latches. Old data can be retained or
new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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