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SN74ALVTH32373KR PDF预览

SN74ALVTH32373KR

更新时间： 2024-11-20 02:58:51
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理输出元件逻辑集成电路
页数 文件大小 规格书
10页 185K
描述
2.5-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74ALVTH32373KR 技术参数

生命周期：Lifetime Buy零件包装代码：BGA
包装说明：LFBGA, BGA96,6X16,32针数：96
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.5
其他特性：ALSO OPERATES AT 3.3V SUPPLY控制类型：ENABLE LOW/HIGH
系列：ALVTJESD-30 代码：R-PBGA-B96
JESD-609代码：e0长度：13.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A湿度敏感等级：2
位数：8功能数量：4
端口数量：2端子数量：96
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA96,6X16,32封装形状：RECTANGULAR
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：235电源：3.3 V
最大电源电流（ICC）：5 mAProp。Delay @ Nom-Sup：3.3 ns
传播延迟（tpd）：4.5 ns认证状态：Not Qualified
座面最大高度：1.4 mm子类别：Bus Driver/Transceiver
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：5.5 mmBase Number Matches：1

SN74ALVTH32373KR 数据手册

 浏览型号SN74ALVTH32373KR的Datasheet PDF文件第2页浏览型号SN74ALVTH32373KR的Datasheet PDF文件第3页浏览型号SN74ALVTH32373KR的Datasheet PDF文件第4页浏览型号SN74ALVTH32373KR的Datasheet PDF文件第5页浏览型号SN74ALVTH32373KR的Datasheet PDF文件第6页浏览型号SN74ALVTH32373KR的Datasheet PDF文件第7页 
SN54ALVTH32373, SN74ALVTH32373  
2.5-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCES322A – FEBRUARY 2000 – REVISED APRIL 2000  
State-of-the-Art Advanced BiCMOS  
Auto3-State Eliminates Bus Current  
Technology (ABT) Widebus+ Design for  
2.5-V and 3.3-V Operation and Low  
Static-Power Dissipation  
Loading When Output Exceeds V  
+ 0.5 V  
CC  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
3.6-V V  
)
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
High Drive (–24/24 mA at 2.5-V and  
–32/64 mA at 3.3-V V  
)
CC  
I
and Power-Up 3-State Support Hot  
– 1000-V Charged-Device Model (C101)  
off  
Insertion  
Packaged in Plastic Fine-Pitch Ball Grid  
Array Package  
Use Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
NOTE: For tape and reel order entry:  
The GKER package is abbreviated to KR.  
description  
The’ALVTH32373devicesare32-bittransparentD-typelatcheswith3-stateoutputsdesignedfor2.5-Vor3.3-V  
operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices  
V
CC  
are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
These devices can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable  
(LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at  
the levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
When V is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+ is a trademark of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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