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SN74AS00NE4 PDF预览

SN74AS00NE4

更新时间: 2024-11-04 14:08:19
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 679K
描述
Quadruple 2-Input Positive-NAND Gates 14-PDIP 0 to 70

SN74AS00NE4 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.15Is Samacsys:N
系列:ASJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.02 A功能数量:4
输入次数:2端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):17.4 mA
传播延迟(tpd):4 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74AS00NE4 数据手册

 浏览型号SN74AS00NE4的Datasheet PDF文件第2页浏览型号SN74AS00NE4的Datasheet PDF文件第3页浏览型号SN74AS00NE4的Datasheet PDF文件第4页浏览型号SN74AS00NE4的Datasheet PDF文件第5页浏览型号SN74AS00NE4的Datasheet PDF文件第6页浏览型号SN74AS00NE4的Datasheet PDF文件第7页 
ꢊ ꢋꢄꢌꢍ ꢋꢎꢅ ꢏꢈ ꢐꢑꢒ ꢁꢎ ꢋꢓ ꢈꢎꢔ ꢀ ꢒꢓ ꢒꢕꢏ ꢑꢁꢄꢁꢌ ꢈ ꢖꢄꢓꢏ  
SDAS187A − APRIL 1982 − REVISED DECEMBER 1994  
SN54ALS00A, SN54AS00 . . . J PACKAGE  
SN74ALS00A, SN74AS00 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
These devices contain four independent 2-input  
positive-NAND gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2Y  
GND  
8
The SN54ALS00A and SN54AS00 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS00A and SN74AS00 are characterized  
for operation from 0°C to 70°C.  
SN54ALS00A, SN54AS00 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
H
X
L
H
L
L
H
H
NC  
2B  
9 10 11 12 13  
X
logic symbol  
1
1A  
2
NC − No internal connection  
&
3
6
1Y  
2Y  
3Y  
4Y  
1B  
4
2A  
5
2B  
9
3A  
10  
3B  
12  
4A  
13  
4B  
8
11  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
ꢓꢣ  
Copyright 1994, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢞꢜ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

SN74AS00NE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS00N TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74AS08N TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-AND GATES
SN74AS02N TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

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AS SERIES, QUAD 2-INPUT NOR GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14
SN74AS02DR TI

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QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SN74AS02DRG4 TI

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AS SERIES, QUAD 2-INPUT NOR GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14