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SN74AS02DRG4 PDF预览

SN74AS02DRG4

更新时间: 2024-11-19 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
18页 1029K
描述
AS SERIES, QUAD 2-INPUT NOR GATE, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14

SN74AS02DRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.43系列:AS
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm逻辑集成电路类型:NOR GATE
最大I(ol):0.02 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):20.1 mA
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):4.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

SN74AS02DRG4 数据手册

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ꢋ ꢌꢄꢍꢎ ꢌꢏꢅ ꢐꢉ ꢇꢑꢒ ꢁꢏꢌ ꢓ ꢉꢏꢔ ꢀ ꢒꢓ ꢒꢕꢐ ꢑꢁꢔꢎ ꢉ ꢖ ꢄꢓꢐ ꢀ  
SDAS111B − APRIL 1982 − REVISED DECEMBER 1994  
SN54ALS02A, SN54AS02 . . . J PACKAGE  
SN74ALS02A, SN74AS02 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1Y  
1A  
1B  
2Y  
2A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4Y  
4B  
4A  
3Y  
3B  
3A  
description  
These devices contain four independent 2-input  
positive-NOR gates. They perform the Boolean  
functions Y = A + B or Y = A B in positive logic.  
2B  
GND  
8
The SN54ALS02A and SN54AS02 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS02A and SN74AS02 are characterized  
for operation from 0°C to 70°C.  
SN54ALS02A, SN54AS02 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1B  
NC  
2Y  
4B  
NC  
4A  
NC  
3Y  
4
5
6
7
8
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
L
L
NC  
2A  
9 10 11 12 13  
H
NC − No internal connection  
logic symbol  
logic diagram (positive logic)  
2
1A  
3
2
1A  
3
1
4
1  
1
4
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
5
1B  
5
2A  
6
2A  
6
2B  
8
2B  
8
3A  
9
10  
13  
3A  
9
10  
13  
3B  
11  
3B  
11  
4A  
12  
4B  
4A  
12  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
ꢓꢤ  
Copyright 1994, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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