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SN74AS00D PDF预览

SN74AS00D

更新时间: 2024-11-03 22:59:15
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
6页 97K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN74AS00D 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SO-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.28Is Samacsys:N
系列:ASJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.02 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):17.4 mA
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):4 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

SN74AS00D 数据手册

 浏览型号SN74AS00D的Datasheet PDF文件第2页浏览型号SN74AS00D的Datasheet PDF文件第3页浏览型号SN74AS00D的Datasheet PDF文件第4页浏览型号SN74AS00D的Datasheet PDF文件第5页浏览型号SN74AS00D的Datasheet PDF文件第6页 
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SDAS187A – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS00A, SN54AS00 . . . J PACKAGE  
SN74ALS00A, SN74AS00 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
These devices contain four independent 2-input  
positive-NAND gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2Y  
GND  
8
The SN54ALS00A and SN54AS00 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS00A and SN74AS00 are characterized  
for operation from 0°C to 70°C.  
SN54ALS00A, SN54AS00 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
H
X
L
H
L
L
H
H
NC  
2B  
9 10 11 12 13  
X
logic symbol  
1
1A  
2
NC – No internal connection  
&
3
6
1Y  
2Y  
3Y  
4Y  
1B  
4
2A  
5
2B  
9
3A  
10  
3B  
12  
4A  
13  
4B  
8
11  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AS00D 替代型号

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