5秒后页面跳转
捷配首页

Datasheet > SN74ALS29854DWE4
SN74ALS29854DWE4 PDF预览

SN74ALS29854DWE4

更新时间： 2024-09-14 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 373K
描述
ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24

阅读下载

中文翻译

获取价格

SN74ALS29854DWE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：compliant风险等级：5.49
其他特性：PARITY GENERATION A TO B; ERROR DETECTION B TO A; ODD PARITY控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ALS
JESD-30 代码：R-PDSO-G24长度：15.4 mm
负载电容（CL）：300 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
最大电源电流（ICC）：100 mAProp。Delay @ Nom-Sup：8 ns
传播延迟（tpd）：13 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.5 mm
Base Number Matches：1

SN74ALS29854DWE4 数据手册

 浏览型号SN74ALS29854DWE4的Datasheet PDF文件第2页浏览型号SN74ALS29854DWE4的Datasheet PDF文件第3页浏览型号SN74ALS29854DWE4的Datasheet PDF文件第4页浏览型号SN74ALS29854DWE4的Datasheet PDF文件第5页浏览型号SN74ALS29854DWE4的Datasheet PDF文件第6页浏览型号SN74ALS29854DWE4的Datasheet PDF文件第7页 
SN74ALS29854  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER  
SDAS118C – FEBRUARY 1987 – REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Similar to AMD’s AM29854  
• High-Speed Bus Transceiver With Parity  
Generator/Checker  
OEA  
A1  
V
CC  
B1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
• Parity-Error Flag With Open-Collector  
2
Outputs  
A2  
B2  
3
• Latch for Storing the Parity-Error Flag  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
A3  
B3  
4
A4  
B4  
5
A5  
B5  
6
A6  
B6  
7
A7  
B7  
8
description  
A8  
B8  
9
ERR  
CLR  
PARITY  
OEB  
10  
11  
The SN74ALS29854 is an 8-bit to 9-bit parity  
transceiver designed for two-way communication  
between data buses. When data is transmitted  
from the A bus to the B bus, a parity bit is  
GND 12  
13 LE  
generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error  
(ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs  
can be used to disable the device so that the buses are effectively isolated.  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with an open-collector ERR flag. ERR can be either passed, sampled, stored, or cleared from the latch using  
the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from  
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the  
designer more system diagnostic capability.  
The SN74ALS29854 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
LE  
OUTPUT AND I/O  
†
Bi  
∑ of Ls  
OPERATION  
Ai  
∑ of Hs  
‡
A
NA  
B
B
A
PARITY  
OEB  
L
OEA  
H
CLR  
X
ERR  
Odd  
Even  
H
L
X
L
NA  
NA  
A data to B bus and generate parity  
B data to A bus and check parity  
Odd  
Even  
H
L
H
L
X
NA  
NA  
NA  
H
X
L
H
L
H
H
NA  
X
X
X
X
X
NA  
NA  
NA  
NA  
N-1  
H
Store error flag  
X
Clear error-flag register  
H
L
X
X
H
H
L
X
X
NC  
H
L
§
Isolation  
H
L
H
L
X
Z
Z
A
Z
L Odd  
H Even  
L
H
Odd  
Even  
L
H
A data to B bus and generate inverted  
parity  
X
X
NA  
NA  
NA  
NA = not applicable, NC = no change, X = don’t care  
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.  
Output states shown assume ERR was previously high.  
In this mode, ERR, when enabled, shows inverted parity of the A bus.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

SN74ALS29854DWE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS29854DWG4 TI

完全替代

 ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24

与SN74ALS29854DWE4相关器件

型号 品牌 获取价格 描述 数据表
SN74ALS29854DWG4 TI

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24
SN74ALS29854DWR TI

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24
SN74ALS29854DWR ROCHESTER

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24
SN74ALS29854DWRE4 TI

获取价格

 		IC ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDSO24, PLASTIC, SO-24, Bus Driver/Tran
SN74ALS29854FN TI

获取价格

 		IC,BUS TRANSCEIVER,SINGLE,8-BIT,ALS-TTL,LDCC,PLASTIC
SN74ALS29854NT TI

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, DIP-24
SN74ALS29854NT ROCHESTER

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, DIP-24
SN74ALS29854NT3 TI

获取价格

 		8-Bit To 9-Bit Parity Bus Transceivers 24-PDIP 0 to 70
SN74ALS29854NT3 ROCHESTER

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, DIP-24
SN74ALS29854NTE4 TI

获取价格

 		ALS SERIES, 8-BIT TRANSCEIVER, INVERTED OUTPUT, PDIP24, 0.300 INCH, PLASTIC, DIP-24

与SN74ALS29854DWE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证