SN74ACT7813DLR

更新时间： 2024-11-16 13:13:47

品牌	Logo	应用领域
德州仪器 - TI		存储
页数	文件大小	规格书
14页	196K
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SN74ACT7813DLR 数据手册

SN74ACT7813

64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS199B – JANUARY 1991 – REVISED APRIL 1998

DL PACKAGE

(TOP VIEW)

Member of the Texas Instruments

Widebus Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

RESET

D17

D16

D15

D14

D13

D12

D11

OE1

Q17

Q16

Q15

GND

Q14

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

Q13

Q12

Q11

Q10

D10

64 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

GND

Bidirectional Configuration and Width

Expansion Without Additional Logic

D6 15

D5 16

D4 17

D3 18

42 Q7

41 Q6

40 Q5

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7803

and SN74ACT7805

GND

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

PEN

AF/AE

WRTCLK

WRTEN2

WRTEN1

RDCLK

RDEN

OE2

description

The SN74ACT7813 is a 64-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V

and

GND pins, along with Texas Instruments patented output edge control (OEC ) circuit, dampen simultaneous

switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless

of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and OEC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...14

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与SN74ACT7813DLR相关器件

型号	品牌	获取价格	描述	数据表
SN74ACT7814	TI	获取价格	64 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-20DL	TI	获取价格	64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-20DLR	TI	获取价格	64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-25DL	TI	获取价格	64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-40DL	TI	获取价格	64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814-40DLR	TI	获取价格	64 x 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7814DL	TI	获取价格	64 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7881	TI	获取价格	1024 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7881-15FN	TI	获取价格	1024 x 18 synchronous FIFO memory 68-PLCC 0 to 70
SN74ACT7881-15FNR	TI	获取价格	1KX18 OTHER FIFO, 12ns, PQCC68, GREEN, PLASTIC, LCC-68

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