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SN74ACT7803-40DLR PDF预览

SN74ACT7803-40DLR

更新时间： 2024-11-15 22:20:23
品牌 Logo 应用领域
德州仪器 - TI 存储
页数 文件大小 规格书
16页 239K
描述
512 ?18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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SN74ACT7803-40DLR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.71
Factory Lead Time：1 week风险等级：5.77
最长访问时间：20 ns最大时钟频率 (fCLK)：25 MHz
周期时间：40 nsJESD-30 代码：R-PDSO-G56
长度：18.415 mm内存密度：9216 bit
内存集成电路类型：OTHER FIFO内存宽度：18
功能数量：1端子数量：56
字数：512 words字数代码：512
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：512X18
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：2.79 mm
最大待机电流：0.0004 A子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

SN74ACT7803-40DLR 数据手册

 浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第2页浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第3页浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第4页浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第5页浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第6页浏览型号SN74ACT7803-40DLR的Datasheet PDF文件第7页 
SN74ACT7803  
512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY  
SCAS191C – MARCH 1991 – REVISED APRIL 1998  
DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Free-Running Read and Write Clocks Can  
Be Asynchronous or Coincident  
RESET  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
OE1  
Q17  
Q16  
Q15  
GND  
Q14  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
2
Read and Write Operations Synchronized  
to Independent System Clocks  
3
4
Input-Ready Flag Synchronized to Write  
Clock  
5
6
V
7
Output-Ready Flag Synchronized to Read  
Clock  
CC  
Q13  
Q12  
Q11  
Q10  
Q9  
8
D10  
9
512 Words by 18 Bits  
V
10  
11  
12  
13  
14  
CC  
Low-Power Advanced CMOS Technology  
D9  
D8  
GND  
D7  
Half-Full Flag and Programmable  
Almost-Full/Almost-Empty Flag  
GND  
Q8  
Bidirectional Configuration and Width  
Expansion Without Additional Logic  
D6 15  
42 Q7  
D5  
D4  
Q6  
Q5  
V
16  
17  
41  
40  
39  
Fast Access Times of 12 ns With a 50-pF  
Load and All Data Outputs Switching  
Simultaneously  
D3 18  
D2 19  
CC  
38 Q4  
Data Rates up to 67 MHz  
37 Q3  
D1 20  
Pin-to-Pin Compatible With SN74ACT7805  
and SN74ACT7813  
36 Q2  
D0 21  
35 GND  
34 Q1  
HF 22  
Packaged in Shrink Small-Outline 300-mil  
Package Using 25-mil Center-to-Center  
Spacing  
PEN 23  
AF/AE 24  
WRTCLK 25  
WRTEN2 26  
WRTEN1 27  
IR 28  
33 Q0  
32 RDCLK  
31 RDEN  
30 OE2  
29 OR  
description  
The SN74ACT7803 is a 512-word × 18-bit FIFO  
suited for buffering asynchronous datapaths up to  
67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering  
without additional logic. Multiple distributed V and GND pins, along with Texas Instruments patented output  
CC  
edge control (OEC ) circuit, dampen simultaneous switching noise.  
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.  
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input  
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low  
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,  
regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output  
buffer.  
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four  
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes  
the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be  
reset upon power up.  
The SN74ACT7803 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and OEC are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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SN74ACT7803-40DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC7803-40DL TI

类似代替

 512X18 OTHER FIFO, 20ns, PDSO56, 0.300 INCH, SSOP-56
SN74ACT7803-25DLR TI

类似代替

 512 ?18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7803-20DL TI

类似代替

 512 ?18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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