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SN74ACT7805-20DLR PDF预览

SN74ACT7805-20DLR

更新时间： 2024-10-02 05:17:59
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路光电二极管先进先出芯片时钟
页数 文件大小 规格书
14页 195K
描述
256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

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SN74ACT7805-20DLR 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SSOP包装说明：GREEN, PLASTIC, SSOP-56
针数：56Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.71
Factory Lead Time：1 week风险等级：5.8
Is Samacsys：N最长访问时间：13 ns
最大时钟频率 (fCLK)：50 MHz周期时间：20 ns
JESD-30 代码：R-PDSO-G56长度：18.415 mm
内存密度：4608 bit内存集成电路类型：OTHER FIFO
内存宽度：18功能数量：1
端子数量：56字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256X18输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：2.79 mm最大待机电流：0.0004 A
子类别：FIFOs最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

SN74ACT7805-20DLR 数据手册

 浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第2页浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第3页浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第4页浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第5页浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第6页浏览型号SN74ACT7805-20DLR的Datasheet PDF文件第7页 
SN74ACT7805  
256 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY  
SCAS201B – MARCH 1991 – REVISED APRIL 1998  
DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Free-Running Read and Write Clocks Can  
Be Asynchronous or Coincident  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
RESET  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
OE1  
Q17  
Q16  
Q15  
GND  
Q14  
2
Read and Write Operations Synchronized  
to Independent System Clocks  
3
4
Input-Ready Flag Synchronized to Write  
Clock  
5
6
7
V
Output-Ready Flag Synchronized to Read  
Clock  
CC  
8
Q13  
Q12  
Q11  
Q10  
Q9  
GND  
Q8  
Q7  
9
D10  
256 Words by 18 Bits  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
V
CC  
D9  
Low-Power Advanced CMOS Technology  
Half-Full Flag and Programmable  
Almost-Full/Almost-Empty Flag  
D8  
GND  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Bidirectional Configuration and Width  
Expansion Without Additional Logic  
Q6  
Q5  
Fast Access Times of 12 ns With a 50-pF  
Load and All Data Outputs Switching  
Simultaneously  
V
CC  
Q4  
Q3  
Q2  
GND  
Q1  
Data Rates up to 67 MHz  
Pin-to-Pin Compatible With SN74ACT7803  
and SN74ACT7813  
D0  
HF  
Packaged in Shrink Small-Outline 300-mil  
Package Using 25-mil Center-to-Center  
Spacing  
PEN  
AF/AE  
WRTCLK  
WRTEN2  
WRTEN1  
IR  
Q0  
RDCLK  
RDEN  
OE2  
OR  
description  
TheSN74ACT7805isa256-word×18-bitclocked  
FIFO suited for buffering asynchronous data  
paths up to 67-MHz clock rates and 12-ns access  
times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed  
and GND pins, along with Texas Instruments patented output edge control (OEC ) circuit, dampen  
V
CC  
simultaneous switching noise.  
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.  
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2is low, and IR is high.  
Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and OR is high.  
The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2  
levels. The OR flag indicates that valid data is present on the output buffer.  
The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four  
WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes  
the input-ready (IR), output-ready (OR), and half-full (HF) flags low and the almost-full/almost-empty (AF/AE)  
flag high. The FIFO must be reset upon power up.  
The SN74ACT7805 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and OEC are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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SN74ACT7805-20DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVC7805-20DLR TI

类似代替

 256X18 OTHER FIFO, 13ns, PDSO56, 0.300 INCH, 0.635 MM PITCH, GREEN, PLASTIC, SSOP-56
SN74ALVC7806-40DL TI

功能相似

 256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY
SN74ALVC7806-25DL TI

功能相似

 256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY

与SN74ACT7805-20DLR相关器件

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SN74ACT7805-25DL TI

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 		256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7805-25DLR TI

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 		256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7805-40DL TI

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 		256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7805-40DLR TI

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 		256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7805DL TI

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 		256 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7805DLR TI

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 		256X18 OTHER FIFO, PDSO56
SN74ACT7806 TI

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 		256 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7806_06 TI

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 		256 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7806-20DL TI

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 		256 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY
SN74ACT7806-20DLR TI

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 		256 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY

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