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SN74ACT7807-15PMR PDF预览

SN74ACT7807-15PMR

更新时间: 2024-11-16 15:52:03
品牌 Logo 应用领域
德州仪器 - TI 先进先出芯片
页数 文件大小 规格书
20页 295K
描述
2KX9 OTHER FIFO, 12ns, PQFP64, PLASTIC, LQFP-64

SN74ACT7807-15PMR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:64
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.76
最长访问时间:12 ns周期时间:15 ns
JESD-30 代码:S-PQFP-G64长度:10 mm
内存密度:18432 bit内存宽度:9
功能数量:1端子数量:64
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX9
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

SN74ACT7807-15PMR 数据手册

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SN74ACT7807  
2048 × 9  
CLOCKED FIRST-IN, FIRST-OUT MEMORY  
SCAS200D – JANUARY 1991 – REVISED APRIL 1998  
Free-Running Read and Write Clocks Can  
Be Asynchronous or Coincident  
Input-Ready, Output-Ready, and Half-Full  
Flags  
Read and Write Operations Synchronized  
to Independent System Clocks  
Cascadable in Word Width and/or Word  
Depth  
Input-Ready Flag Synchronized to Write  
Clock  
Fast Access Times of 12 ns With a 50-pF  
Load  
Output-Ready Flag Synchronized to Read  
Clock  
Data Rates up to 67 MHz  
3-State Outputs  
2048 Words by 9 Bits  
Package Options Include 44-Pin Plastic  
Leaded Chip Carrier (FN) and 64-Pin Thin  
Quad Flat (PAG, PM) Packages  
Low-Power Advanced CMOS Technology  
Programmable Almost-Full/Almost-Empty  
Flag  
description  
The SN74ACT7807 is a 2048-word by 9-bit FIFO with high speed and fast access times. It processes data at  
rates up to 67 MHz and access times of 12 ns in a bit-parallel format. Data outputs are noninverting with respect  
to the data inputs. Expansion is easily accomplished in both word width and word depth.  
The write-clock (WRTCLK) and read-clock (RDCLK) inputs should be free running and can be asynchronous  
or coincident. Data is written to memory on the rising edge of WRTCLK when the write-enable (WRTEN1/DP9,  
WRTEN2) inputs are high and the input-ready (IR) flag output is high. Data is read from memory on the rising  
edge of RDCLK when the read-enable (RDEN1, RDEN2) and output-enable (OE) inputs are high and the  
output-ready (OR) flag output is high. The first word written to memory is clocked through to the output buffer  
regardless of the levels on RDEN1, RDEN2, and OE. The OR flag indicates that valid data is present on the  
output buffer.  
The FIFO can be reset asynchronous to WRTCLK and RDCLK. RESET must be asserted while at least four  
WRTCLK and four RDCLK cycles occur to clear the synchronizing registers. Resetting the FIFO initializes the  
IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset  
upon power up.  
The SN74ACT7807 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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