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SN74ACT7804-20DLR PDF预览

SN74ACT7804-20DLR

更新时间： 2024-10-02 05:17:59
品牌 Logo 应用领域
德州仪器 - TI 存储
页数 文件大小 规格书
13页 184K
描述
512 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY

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SN74ACT7804-20DLR 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71Factory Lead Time：1 week
风险等级：8.39最长访问时间：20 ns
最大时钟频率 (fCLK)：50 MHz周期时间：20 ns
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm内存密度：9216 bit
内存集成电路类型：OTHER FIFO内存宽度：18
湿度敏感等级：1功能数量：1
端子数量：56字数：512 words
字数代码：512工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：512X18输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：2.79 mm子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.5 mm
Base Number Matches：1

SN74ACT7804-20DLR 数据手册

 浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第2页浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第3页浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第4页浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第5页浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第6页浏览型号SN74ACT7804-20DLR的Datasheet PDF文件第7页 
SN74ACT7804  
512 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY  
SCAS204C – APRIL 1992 – REVISED APRIL 1998  
DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Load Clock and Unload Clock Can Be  
Asynchronous or Coincident  
RESET  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
OE  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
Q17  
Q16  
Q15  
GND  
Q14  
2
512 Words by 18 Bits  
3
Low-Power Advanced CMOS Technology  
Full, Empty, and Half-Full Flags  
4
5
6
Programmable Almost-Full/Almost-Empty  
Flag  
V
7
CC  
Q13  
Q12  
8
Fast Access Times of 15 ns With a 50-pF  
Load and All Data Outputs Switching  
Simultaneously  
D10  
9
V
10  
11  
12  
47 Q11  
CC  
D9  
Q10  
Q9  
46  
45  
Data Rates up to 50 MHz  
3-State Outputs  
D8  
GND 13  
D7 14  
44 GND  
43 Q8  
42 Q7  
41 Q6  
40 Q5  
Pin-to-Pin Compatible With SN74ACT7806  
and SN74ACT7814  
D6 15  
D5 16  
Packaged in Shrink Small-Outline 300-mil  
Package Using 25-mil Center-to-Center  
Spacing  
D4 17  
D3 18  
39  
V
CC  
D2 19  
38 Q4  
D1 20  
37 Q3  
description  
D0 21  
36 Q2  
A FIFO memory is a storage device that allows  
data to be written into and read from its array at  
independent data rates. The SN74ACT7804 is a  
512-word by 18-bit FIFO for high speed and fast  
access times. It processes data at rates up to  
50 MHz and access times of 15 ns in a bit-parallel  
format.  
HF 22  
35 GND  
34 Q1  
PEN 23  
AF/AE 24  
LDCK 25  
NC 26  
NC 27  
FULL 28  
33 Q0  
32 UNCK  
31 NC  
30 NC  
29 EMPTY  
Data is written into memory on a low-to-high  
transition at the load-clock (LDCK) input and is  
read out on a low-to-high transition at the  
unload-clock (UNCK) input. The memory is full  
when the number of words clocked in exceeds the  
number of words clocked out by 512. When the  
memory is full, LDCK signals have no effect on the  
data residing in memory. When the memory is  
empty, UNCK signals have no effect.  
NC – No internal connection  
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and  
almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the  
memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF  
output is high when the FIFO contains 256 or more words. The AF/AE status flag is a programmable flag. The  
first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value  
(X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO  
contains X or fewer words or (512 – Y) or more words. The AF/AE flag is low when the FIFO contains between  
(X + 1) and (511 – Y) words.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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SN74ACT7804-20DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT7804-20DL TI

类似代替

 512 】 18 STROBED FIRST-IN, FIRST-OUT MEMORY

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