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SN74AC11651NT

更新时间： 2024-09-15 15:52:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
10页 148K
描述
AC SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP28, 0.300 INCH, PLASTIC, DIP-28

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SN74AC11651NT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：28
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：AC
JESD-30 代码：R-PDIP-T28长度：35.69 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：19.2 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN74AC11651NT 数据手册

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SCAS135 − MARCH 1990 − REVISED APRIL 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• Independent Registers and Enables for A  
and B Buses  
• Multiplexed Real-Time and Stored Data  
• Inverting Data Paths  
OEAB  
A1  
CLKAB  
SAB  
B1  
1
2
3
4
5
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9
28  
27  
26  
25  
• Flow-Through Architecture Optimizes PCB  
A2  
A3  
A4  
GND  
GND  
GND  
GND  
Layout  
B2  
24 B3  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
B4  
23  
22  
21  
V
V
CC  
CC  
•
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
20 B5  
• 500-mA Typical Latch-Up Immunity at  
A5 10  
A6 11  
19 B6  
125°C  
18 B7  
• Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
A7 12  
17 B8  
A8 13  
16 CLKBA  
15 SBA  
OEBA 14  
description  
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and  
OEBA) inputs are provided to control the transceiver functions. The select-control (SAB and SBA) inputs are  
provided to select whether real-time or stored data is transferred. A low input level selects real-time data, and  
a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that  
can be performed with the 74AC11651.  
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the  
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and  
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops  
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when  
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.  
The 74AC11651 is characterized for operation from −40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
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Copyright 1993, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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