ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢆꢇ ꢈ ꢉ
ꢊ ꢋꢌꢉ ꢍꢈ ꢎ ꢇꢌꢁ ꢉꢏꢊ ꢉꢐ ꢀꢌ ꢊ ꢌꢑꢈ ꢇꢄ ꢁꢒ ꢓ ꢄꢊꢈ
SCLS557 − JANUARY 2004
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
2-V to 6-V V
Operation
CC
Inputs Accept Voltages to 6 V
Max t of 7.5 ns at 5 V
pd
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D OR PW PACKAGE
(TOP VIEW)
D
Enhanced Product-Change Notification
†
D
Qualification Pedigree
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
2A
2B
2C
V
CC
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1C
1Y
3A
3B
3C
3Y
2Y
GND
8
description/ordering information
The SN74AC11 device contains three independent 3-input AND gates. This device performs the Boolean
function Y = A • B • C or Y = A + B + C in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
§
SOIC − D
Tape and reel
Tape and reel
SN74AC11IDREP
SAC11EP
SAC11EP
−40°C to 85°C
TSSOP − PW
SN74AC11IPWREP
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Product Preview
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
C
H
X
X
L
H
L
L
L
X
X
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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