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SN74ABT841ANT

更新时间： 2024-11-17 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件信息通信管理PC
页数 文件大小 规格书
7页 112K
描述
10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74ABT841ANT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：PLASTIC, DIP-24针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：7.32
Samacsys Confidence：Samacsys Status：Released
Samacsys PartID：605004Samacsys Pin Count：24
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Other
Samacsys Footprint Name：DIP254P762X508-24Samacsys Released Date：2017-01-12 12:59:53
Is Samacsys：N系列：ABT
JESD-30 代码：R-PDIP-T24JESD-609代码：e4
长度：31.64 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
位数：10功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：38 mAProp。Delay @ Nom-Sup：6.2 ns
传播延迟（tpd）：6.7 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

SN74ABT841ANT 数据手册

 浏览型号SN74ABT841ANT的Datasheet PDF文件第2页浏览型号SN74ABT841ANT的Datasheet PDF文件第3页浏览型号SN74ABT841ANT的Datasheet PDF文件第4页浏览型号SN74ABT841ANT的Datasheet PDF文件第5页浏览型号SN74ABT841ANT的Datasheet PDF文件第6页浏览型号SN74ABT841ANT的Datasheet PDF文件第7页 
SN54ABT841, SN74ABT841A  
10-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS196D – FEBRUARY 1991 – REVISED MAY 1997  
SN54ABT841 . . . JT OR W PACKAGE  
SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 LE  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
9D 10  
10D 11  
GND 12  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
SN54ABT841 . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1 28 27 26  
25  
The SN54ABT841 and SN74ABT841A 10-bit  
latches are designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
5
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
6
24  
23  
22  
21  
20  
19  
7
8
9
10  
11  
The ten transparent D-type latches provide true  
data at their outputs.  
12 13 14 15 16 17 18  
A buffered output-enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low logic levels) or  
a
NC – No internal connection  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT841A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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SN74ABT841ANT 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT841ADW TI

完全替代

 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT841ADWR TI

类似代替

 10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841ADWG4 TI

类似代替

 10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS

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SN74ABT841APW TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT841APWE4 TI

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SN74ABT841APWG4 TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841APWLE TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841APWR TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841APWRE4 TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841APWRG4 TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS
SN74ABT841DB TI

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 		IC ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, SSOP-24, Bus Driver/Transceiver
SN74ABT841DBLE TI

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 		暂无描述

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