5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ABT841APWRG4
SN74ABT841APWRG4 PDF预览

SN74ABT841APWRG4

更新时间： 2024-11-18 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
21页 788K
描述
10-BIT BUS-INTERFACE D-TYPE LATCHES ITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ABT841APWRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-24针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61Is Samacsys：N
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：10
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：38 mA
Prop。Delay @ Nom-Sup：6.2 ns传播延迟（tpd）：6.7 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74ABT841APWRG4 数据手册

 浏览型号SN74ABT841APWRG4的Datasheet PDF文件第2页浏览型号SN74ABT841APWRG4的Datasheet PDF文件第3页浏览型号SN74ABT841APWRG4的Datasheet PDF文件第4页浏览型号SN74ABT841APWRG4的Datasheet PDF文件第5页浏览型号SN74ABT841APWRG4的Datasheet PDF文件第6页浏览型号SN74ABT841APWRG4的Datasheet PDF文件第7页 
SN54ABT841, SN74ABT841A  
10-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS196D – FEBRUARY 1991 – REVISED MAY 1997  
SN54ABT841 . . . JT OR W PACKAGE  
SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 LE  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Impedance State During Power Up  
and Power Down  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
9D 10  
10D 11  
GND 12  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
SN54ABT841 . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1 28 27 26  
25  
The SN54ABT841 and SN74ABT841A 10-bit  
latches are designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
5
3D  
4D  
5D  
NC  
6D  
7D  
8D  
3Q  
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
6
24  
23  
22  
21  
20  
19  
7
8
9
10  
11  
The ten transparent D-type latches provide true  
data at their outputs.  
12 13 14 15 16 17 18  
A buffered output-enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low logic levels) or  
a
NC – No internal connection  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT841A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

中文翻译

下载PDF

与SN74ABT841APWRG4相关器件

型号 品牌 获取价格 描述 数据表
SN74ABT841DB TI

获取价格

 		IC ABT SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, SSOP-24, Bus Driver/Transceiver
SN74ABT841DBLE TI

获取价格

 		暂无描述
SN74ABT841DWR TI

获取价格

 		10-Bit Bus-Interface D-Type Latches With 3-State Outputs 24-SOIC -40 to 85
SN74ABT841NT TI

获取价格

 		暂无描述
SN74ABT843 TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT843DB TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT843DBLE TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT843DBR TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT843DBRE4 TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74ABT843DBRG4 TI

获取价格

 		9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

与SN74ABT841APWRG4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证