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SN74ABT843

更新时间： 2024-09-16 23:06:11
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德州仪器 - TI 锁存器输出元件
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9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74ABT843 数据手册

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SN54ABT843, SN74ABT843  
9-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS197D – FEBRUARY 1991 – REVISED MAY 1997  
SN54ABT843 . . . JT OR W PACKAGE  
SN74ABT843 . . . DB, DW, OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OE  
1D  
V
CC  
Typical V  
(Output Ground Bounce) < 1 V  
2
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
9Q  
PRE  
LE  
OLP  
at V  
= 5 V, T = 25°C  
3
2D  
3D  
4D  
5D  
CC  
A
4
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
5
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, Ceramic Chip  
Carriers (FK), Ceramic Flat (W) Package,  
and Plastic (NT) and Ceramic (JT) DIPs  
6
7
6D  
7D  
8D  
9D  
8
9
10  
11  
12  
CLR  
GND  
description  
The ’ABT843 9-bit latches are designed  
specifically for driving highly capacitive or  
relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
SN54ABT843 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25 3Q  
The nine transparent D-type latches provide true  
data at the outputs.  
3D  
4D  
5D  
NC  
6D  
7D  
8D  
5
4Q  
5Q  
NC  
6Q  
7Q  
8Q  
6
24  
23  
22  
21  
20  
19  
7
A buffered output-enable (OE) input can be used  
to place the nine outputs in either a normal logic  
8
state (high or low logic levels) or  
a
9
high-impedance state. The outputs are also in the  
high-impedance state during power-up and  
power-downconditions. Theoutputsremaininthe  
high-impedance state while the device is powered  
down. In the high-impedance state, the outputs  
neither load nor drive the bus lines significantly.  
The high-impedance state and increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components.  
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT843 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT843 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

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SN74ABT843 替代型号

型号 品牌 替代类型 描述 数据表
SN54ABT843 TI

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