SN74ABT853

更新时间： 2024-11-20 23:06:11

品牌	Logo	应用领域
德州仪器 - TI		总线收发器
页数	文件大小	规格书
9页	143K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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SN74ABT853 数据手册

SN54ABT853, SN74ABT853

8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997

SN54ABT853 . . . JT OR W PACKAGE

SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

OEA

Latch-Up Performance Exceeds 500 mA Per

JESD 17

Typical V

< 1 V at V

(Output Ground Bounce)

OLP

= 5 V, T = 25°C

High-Drive Outputs (–32-mA I , 64-mA I

)

High-Impedance State During Power Up

and Power Down

ERR 10

15 PARITY

Parity-Error Flag With Parity

Generator/Checker

CLR

GND

OEB

Latch for Storage of Parity-Error Flag

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

SN54ABT853 . . . FK PACKAGE

(TOP VIEW)

28 27 26

description

The ’ABT853 8-bit to 9-bit parity transceivers are

designedforcommunicationbetweendatabuses.

When data is transmitted from the A bus to the

B bus, a parity bit is generated. When data is

transmitted from the B bus to the A bus with its

corresponding parity bit, the open-collector

parity-error (ERR) output indicates whether or not

an error in the B data has occurred. The

output-enable (OEA and OEB) inputs can be used

to disable the device so that the buses are

effectively isolated. The ’ABT853 transceivers

provide true data at their outputs.

12 13 14 15 16 17 18

NC – No internal connection

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the

latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from

the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the

designer more system diagnostic capability.

When V

is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to V

the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup resistor;

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN74ABT853相关器件

型号	品牌	获取价格	描述	数据表
SN74ABT853DB	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN74ABT853DBLE	TI	获取价格	8-Bit To 9-Bit Parity Bus Transceivers 24-SSOP -40 to 85
SN74ABT853DBR	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74ABT853DBRE4	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74ABT853DBRG4	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
SN74ABT853DW	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN74ABT853DWR	TI	获取价格	8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN74ABT853NSR	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74ABT853NSRE4	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
SN74ABT853NSRG4	TI	获取价格	ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24

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