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SN74ABT652ADBR PDF预览

SN74ABT652ADBR

更新时间： 2024-11-11 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
20页 446K
描述
OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN74ABT652ADBR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP24,.3针数：24
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.17其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：8.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP24,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.25 mAProp。Delay @ Nom-Sup：5.4 ns
传播延迟（tpd）：5.6 ns认证状态：Not Qualified
施密特触发器：No座面最大高度：2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：5.3 mmBase Number Matches：1

SN74ABT652ADBR 数据手册

 浏览型号SN74ABT652ADBR的Datasheet PDF文件第2页浏览型号SN74ABT652ADBR的Datasheet PDF文件第3页浏览型号SN74ABT652ADBR的Datasheet PDF文件第4页浏览型号SN74ABT652ADBR的Datasheet PDF文件第5页浏览型号SN74ABT652ADBR的Datasheet PDF文件第6页浏览型号SN74ABT652ADBR的Datasheet PDF文件第7页 
SN54ABT652A, SN74ABT652A  
OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS072F – JANUARY 1991 – REVISED MAY 1997  
SN54ABT652A . . . JT OR W PACKAGE  
SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
CLKBA  
SBA  
OEBA  
B1  
2
3
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
4
A2  
5
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
A3  
B2  
6
= 5 V, T = 25°C  
A
A4  
B3  
7
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
A5  
B4  
8
Package Options Include Plastic  
A6  
B5  
9
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
A7  
B6  
10  
11  
A8  
B7  
GND 12  
13 B8  
SN54ABT652A . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices consist of bus-transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
A1  
A2  
A2  
NC  
A4  
OEBA  
B1  
B2  
NC  
B3  
B4  
Output-enable (OEAB and OEBA) inputs are  
provided to control the transceiver functions.  
Select-control (SAB and SBA) inputs are provided  
to select either real-time or stored data for  
transfer. The circuitry used for select control  
eliminates the typical decoding glitch that occurs  
in a multiplexer during the transition between  
stored and real-time data. A low input selects  
real-time data, and a high input selects stored  
data. Figure 1 illustrates the four fundamental  
bus-management functions that can be  
performed with the ’ABT652A.  
24  
23  
22  
21  
20  
19  
A5 10  
A6 11  
B5  
12 13 14 15 16 17 18  
NC – No internal connection  
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions  
attheappropriateclock(CLKABorCLKBA)inputs, regardlessoftheselect-orenable-controlinputs. WhenSAB  
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops  
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all  
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last  
state.  
To ensure the high-impedance state during power up or power down, OEBA should be tied to V  
through a  
CC  
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver  
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is  
determined by the current-sourcing capability of the driver (A to B).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...20

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SN74ABT652ADBR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT652ADWR TI

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 OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT652ADBRE4 TI

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