Datasheet > SN74ABT3612-15PCBR

SN74ABT3612-15PCBR

更新时间： 2024-11-11 15:52:03

品牌	Logo	应用领域
德州仪器 - TI		先进先出芯片信息通信管理
页数	文件大小	规格书
35页	548K
描述
64X36 BI-DIRECTIONAL FIFO, 10ns, PQFP120, GREEN, PLASTIC, HLQFP-120

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SN74ABT3612-15PCBR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	GREEN, PLASTIC, HLQFP-120	针数：	120
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.78
Is Samacsys：	N	最长访问时间：	10 ns
其他特性：	PARITY GENERATOR/CHECKER; MAILBOX	周期时间：	15 ns
JESD-30 代码：	S-PQFP-G120	长度：	14 mm
内存密度：	2304 bit	内存宽度：	36
功能数量：	1	端子数量：	120
字数：	64 words	字数代码：	64
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64X36
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	HLFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BICMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

SN74ABT3612-15PCBR 数据手册

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SN74ABT3612

64 × 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCBS129G – JULY 1992 – REVISED APRIL 1998

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

EFB, FFB, AEB, and AFB Flags

Synchronized by CLKB

Two Independent 64 × 36 Clocked FIFOs

Passive Parity Checking on Each Port

Buffering Data in Opposite Directions

Parity Generation Can Be Selected for Each

Port

Mailbox-Bypass Register for Each FIFO

Programmable Almost-Full and

Almost-Empty Flags

Low-Power Advanced BiCMOS Technology

Supports Clock Frequencies up to 67 MHz

Fast Access Times of 10 ns

Microprocessor Interface Control Logic

EFA, FFA, AEA, and AFA Flags

Synchronized by CLKA

Package Options Include 120-Pin Thin

Quad Flat (PCB) and 132-Pin Plastic Quad

Flat (PQ) Packages

description

The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock

frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM

FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions

and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is

stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.

Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each

port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or

more devices can be used in parallel to create wider datapaths.

The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asynchronous or coincident. The enables for each port

are arranged to provide a simple bidirectional interface between microprocessors and/or buses with

synchronous control.

The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock

that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are

two-stage synchronized to the port clock that reads data from its array.

The SN74ABT3612 is characterized for operation from 0°C to 70°C.

For more information on this device family, see the following application reports:

FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number

SCAA007)

Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications

(literature number SCAA015)

Metastability Performance of Clocked FIFOs (literature number SCZA004)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...35

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与SN74ABT3612-15PCBR相关器件

型号	品牌	获取价格	描述	数据表
SN74ABT3612-15PQ	TI	获取价格	64 x 36 x 2 bidirectional synchronous FIFO memory 132-BQFP 0 to 70
SN74ABT3612-15PQ	ROCHESTER	获取价格	64X36 BI-DIRECTIONAL FIFO, 10ns, PQFP132, GREEN, PLASTIC, BQFP-132
SN74ABT3612-15PQR	TI	获取价格	64X36 BI-DIRECTIONAL FIFO, 10ns, PQFP132, GREEN, PLASTIC, BQFP-132
SN74ABT3612-20PCB	ROCHESTER	获取价格	64 X 36 BI-DIRECTIONAL FIFO, 12 ns, PQFP120, GREEN, PLASTIC, HLQFP-120
SN74ABT3612-20PCBR	TI	获取价格	64X36 BI-DIRECTIONAL FIFO, 12ns, PQFP120, GREEN, PLASTIC, HLQFP-120
SN74ABT3612-20PQ	ROCHESTER	获取价格	64X36 BI-DIRECTIONAL FIFO, 12ns, PQFP132, GREEN, PLASTIC, BQFP-132
SN74ABT3612-30PCB	ROCHESTER	获取价格	64X36 BI-DIRECTIONAL FIFO, 15ns, PQFP120, GREEN, PLASTIC, HLQFP-120
SN74ABT3612-30PCBR	TI	获取价格	64X36 BI-DIRECTIONAL FIFO, 15ns, PQFP120, GREEN, PLASTIC, HLQFP-120
SN74ABT3612-30PQ	ROCHESTER	获取价格	64X36 BI-DIRECTIONAL FIFO, 15ns, PQFP132, GREEN, PLASTIC, BQFP-132
SN74ABT3612PCB	TI	获取价格	64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, F

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