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SN74ABT3613PQR PDF预览

SN74ABT3613PQR

更新时间: 2024-09-23 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 存储配套器件
页数 文件大小 规格书
32页 460K
描述
64X36 OTHER FIFO, 10ns, PQFP132, QFP-132

SN74ABT3613PQR 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:BQFP,针数:132
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.76
最长访问时间:10 ns周期时间:15 ns
JESD-30 代码:S-PQFP-G132长度:24.13 mm
内存密度:2304 bit内存宽度:36
功能数量:1端子数量:132
字数:64 words字数代码:64
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64X36
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BQFP封装形状:SQUARE
封装形式:FLATPACK, BUMPER并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:4.572 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUAD宽度:24.13 mm
Base Number Matches:1

SN74ABT3613PQR 数据手册

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SN74ABT3613  
64 × 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY  
WITH BUS MATCHING AND BYTE SWAPPING  
SCBS128F – JULY 1992 – REVISED APRIL 1998  
Low-Power Advanced BiCMOS Technology  
Programmable Almost-Full and  
Almost-Empty Flags  
Free-Running CLKA and CLKB Can Be  
Asynchronous or Coincident  
Microprocessor Interface Control Logic  
FF and AF Flags Synchronized by CLKA  
EF and AE Flags Synchronized by CLKB  
Passive Parity Checking on Each Port  
64 × 36 FIFO Buffering Data From Port A to  
Port B  
Mailbox-Bypass Registers in Each  
Direction  
Parity Generation Can Be Selected for Each  
Port  
Dynamic Port-B Bus Sizing of 36 Bits (Long  
Word), 18 Bits (Word), and 9 Bits (Byte)  
Supports Clock Frequencies up to 67 MHz  
Fast Access Times of 10 ns  
Selection of Big- or Little-Endian Format for  
Word and Byte Bus Sizes  
Package Options Include 120-Pin Thin  
Quad Flat (PCB) and 132-Pin Quad Flat  
(PQ) Packages  
Three Modes of Byte-Order Swapping on  
Port B  
description  
The SN74ABT3613 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies  
up to 67 MHz and has read-access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO in this device buffers  
data from port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags  
(almost full and almost empty) to indicate when a selected number of words is stored in memory. FIFO data on  
port B can be output in 36-bit, 18-bit, and 9-bit formats, with a choice of big- or little-endian configurations. Three  
modes of byte-order swapping are possible with any bus-size selection. Communication between each port can  
bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has  
been stored. Parity is checked passively on each port and can be ignored if not desired. Parity generation can  
be selected for data read from each port.  
The SN74ABT3613 is a clocked FIFO, which means each port employs a synchronous interface. All data  
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable  
signals. The continuous clocks for each port are independent of one another and can be asynchronous or  
coincident. The enables for each port are arranged to provide a simple interface between microprocessors  
and/or buses controlled by a synchronous interface.  
The full flag (FF) and almost-full (AF) flag of a FIFO are two-stage synchronized to the port clock that writes data  
to its array. The empty flag (EF) and almost-empty (AE) flag of a FIFO are two-stage synchronized to the port  
clock that reads data from its array.  
The SN74ABT3613 is characterized for operation from 0°C to 70°C.  
For more information on this device family, see the following application reports:  
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control  
(literature number SCAA007)  
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications  
(literature number SCAA014)  
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications  
(literature number SCAA015)  
Internetworking the SN74ABT3614 (literature number SCAA018)  
Metastability Performance of Clocked FIFOs (literature number SCZA004)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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