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SN74ABT16652DLR PDF预览

SN74ABT16652DLR

更新时间: 2024-02-19 14:36:22
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德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
14页 235K
描述
16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

SN74ABT16652DLR 数据手册

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SN54ABT16652, SN74ABT16652  
16-BIT BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCBS215B – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT16652 . . . WD PACKAGE  
SN74ABT16652 . . . DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OEAB  
1CLKAB  
1SAB  
GND  
1OEBA  
1CLKBA  
1SBA  
GND  
1B1  
1B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
2
3
4
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
1A1  
1A2  
5
= 5 V, T = 25°C  
A
6
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
V
7
CC  
CC  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
8
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
High-Drive Outputs (–32-mA I , 64-mA I  
)
OL  
OH  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) Package and  
380-mil Fine-Pitch Ceramic Flat (WD)  
Package Using 25-mil Center-to-Center  
Spacings  
description  
The ’ABT16652 are 16-bit bus transceivers that  
consist of D-type flip-flops and control circuitry  
arranged for multiplexed transmission of data  
directly from the data bus or from the internal  
storage registers. These devices can be used as  
two 8-bit transceivers or one 16-bit transceiver.  
V
V
CC  
CC  
2A7 23  
2A8 24  
34 2B7  
33 2B8  
GND 25  
32 GND  
31 2SBA  
30 2CLKBA  
29 2OEBA  
Output-enable (OEAB and OEBA) inputs are  
provided to control the transceiver functions.  
Select-control (SAB and SBA) inputs are provided  
to select whether real-time or stored data is  
transferred. The circuitry used for select control  
eliminates the typical decoding glitch that occurs  
in a multiplexer during the transition between  
stored and real-time data. A low input selects  
real-time data, and a high input selects stored  
data. Figure 1 illustrates the four fundamental  
bus-management functions that can be  
performed with the ’ABT16652.  
2SAB 26  
2CLKAB 27  
2OEAB 28  
Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions  
at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control inputs. When SAB  
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops  
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all  
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last  
state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ABT16652DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16952DL TI

完全替代

16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT16652DL TI

完全替代

16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
74FCT162652ATPVCT TI

完全替代

16-Bit Registered Transceivers

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