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SN74ABT16823DLR PDF预览

SN74ABT16823DLR

更新时间： 2024-01-12 15:36:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
14页 235K
描述
18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT16823DLR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.07Is Samacsys：N
其他特性：WITH CLEAR AND CLOCK ENABLE计数方向：UNIDIRECTIONAL
系列：ABTJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.41 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.064 A
湿度敏感等级：1位数：9
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：80 mA
Prop。Delay @ Nom-Sup：6.8 ns传播延迟（tpd）：6 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.49 mmBase Number Matches：1

SN74ABT16823DLR 数据手册

 浏览型号SN74ABT16823DLR的Datasheet PDF文件第2页浏览型号SN74ABT16823DLR的Datasheet PDF文件第3页浏览型号SN74ABT16823DLR的Datasheet PDF文件第4页浏览型号SN74ABT16823DLR的Datasheet PDF文件第5页浏览型号SN74ABT16823DLR的Datasheet PDF文件第6页浏览型号SN74ABT16823DLR的Datasheet PDF文件第7页 
SN54ABT16823, SN74ABT16823  
18-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS217C – JUNE 1992 – REVISED JANUARY 1997  
SN54ABT16823 . . . WD PACKAGE  
SN74ABT16823 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1CLR  
1OE  
1Q1  
GND  
1Q2  
1Q3  
1CLK  
1CLKEN  
1D1  
GND  
1D2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
High-Impedance State During Power Up  
and Power Down  
2
3
4
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
5
1D3  
6
V
V
7
CC  
CC  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
8
at V  
= 5 V, T = 25°C  
CC  
A
9
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flow-Through Architecture Optimizes  
PCB Layout  
High-Drive Outputs (–32-mA I  
,
OH  
64-mA I  
)
OL  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2OE  
2CLR  
2D7  
2D8  
GND  
2D9  
2CLKEN  
2CLK  
These 18-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
The ’ABT16823 can be used as two 9-bit flip-flops  
or one 18-bit flip-flop. With the clock-enable  
(CLKEN) input low, the D-type flip-flops enter data  
on the low-to-high transitions of the clock. Taking  
CLKEN high disables the clock buffer, latching the  
outputs. Taking the clear (CLR) input low causes  
the Q outputs to go low independently of the clock.  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

中文翻译

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SN74ABT16823DLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABTH16823DLR TI

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SN74ABT16823DL TI

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