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SN74ABT16821DL PDF预览

SN74ABT16821DL

更新时间： 2024-11-13 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件信息通信管理PC
页数 文件大小 规格书
7页 125K
描述
20-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74ABT16821DL 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SSOP
包装说明：0.300 INCH, GREEN, PLASTIC, SSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.24Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：604971
Samacsys Pin Count：56Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：SOP63P1035X279-56N
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
其他特性：TYP VOLP < 1V @ VCC = 5V, TA = 25 DEG C控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.41 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.064 A湿度敏感等级：1
位数：10功能数量：2
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：89 mAProp。Delay @ Nom-Sup：6.1 ns
传播延迟（tpd）：6.1 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74ABT16821DL 数据手册

 浏览型号SN74ABT16821DL的Datasheet PDF文件第2页浏览型号SN74ABT16821DL的Datasheet PDF文件第3页浏览型号SN74ABT16821DL的Datasheet PDF文件第4页浏览型号SN74ABT16821DL的Datasheet PDF文件第5页浏览型号SN74ABT16821DL的Datasheet PDF文件第6页浏览型号SN74ABT16821DL的Datasheet PDF文件第7页 
SN54ABT16821, SN74ABT16821  
20-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS216B – JUNE 1992 – REVISED JANUARY 1997  
SN54ABT16821 . . . WD PACKAGE  
SN74ABT16821 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2
3
4
Typical V  
(Output Ground Bounce) < 1 V  
5
OLP  
at V  
= 5 V, T = 25°C  
6
CC  
A
V
V
7
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
CC  
CC  
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
8
9
Flow-Through Architecture Optimizes PCB  
Layout  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
High-Drive Outputs (–32-mA I  
,
OH  
64-mA I  
)
OL  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG), 300-mil Shrink  
Small-Outline (DL) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
These 20-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
V
V
CC  
CC  
2Q7  
2Q8  
2D7  
2D8  
GND 25  
32 GND  
2Q9  
2Q10  
2OE  
2D9  
2D10  
2CLK  
26  
27  
28  
31  
30  
29  
The ’ABT16821 can be used as two 10-bit  
flip-flops or one 20-bit flip-flop. The 20 flip-flops  
are edge-triggered D-type flip-flops. On the  
positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high  
or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT16821 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT16821 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

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SN74ABT16821DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16821DLRG4 TI

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