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SN74ABT16657DLRG4 PDF预览

SN74ABT16657DLRG4

更新时间： 2024-02-10 15:47:42
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
10页 182K
描述
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

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中文翻译

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SN74ABT16657DLRG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.51Is Samacsys：N
其他特性：WITH DIRECTION CONTROL控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：18.415 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：5 V最大电源电流（ICC）：36 mA
Prop。Delay @ Nom-Sup：4.3 ns传播延迟（tpd）：4.3 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.5 mm
Base Number Matches：1

SN74ABT16657DLRG4 数据手册

 浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第2页浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第3页浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第4页浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第5页浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第6页浏览型号SN74ABT16657DLRG4的Datasheet PDF文件第7页 
SN54ABT16657, SN74ABT16657  
16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS  
AND 3-STATE OUTPUTS  
SCBS103B – FEBRUARY 1992 – REVISED JANUARY 1997  
SN54ABT16657 . . . WD PACKAGE  
SN74ABT16657 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1OE  
NC  
1ERR  
GND  
1A1  
1
56 1T/R  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
2
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1ODD/EVEN  
1PARITY  
GND  
1B1  
1B2  
3
4
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
5
at V  
= 5 V, T = 25°C  
CC  
A
6
1A2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Flow-Through Architecture Optimizes PCB  
Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’ABT16657 contain two noninverting octal  
transceiver sections with separate parity  
generator/checker circuits and control signals.  
For either section, the transmit/receive (1T/R or  
2T/R) input determines the direction of data flow.  
When 1T/R (or 2T/R) is high, data flows from the  
1A (or 2A) port to the 1B (or 2B) port (transmit  
mode); when 1T/R (or 2T/R) is low, data flows  
from the 1B (or 2B) port to the 1A (or 2A) port  
(receive mode). When the output-enable (1OE or  
2OE) input is high, both the 1A (or 2A) and 1B (or  
2B) ports are in the high-impedance state.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2ERR  
NC  
2B7  
2B8  
GND  
2PARITY  
2ODD/EVEN  
2T/R  
2OE  
NC – No internal connection  
Odd or even parity is selected by a logic high or low level, respectively, on the 1ODD/EVEN (or 2ODD/EVEN)  
input. 1PARITY (or 2PARITY) carries the parity bit value; it is an output from the parity generator/checker in the  
transmit mode and an input to the parity generator/checker in the receive mode.  
In the transmit mode, after the 1A (or 2A) bus is polled to determine the number of high bits, 1PARITY (or  
2PARITY) is set to the logic level that maintains the parity sense selected by the level at the 1ODD/EVEN (or  
2ODD/EVEN) input. For example, if 1ODD/EVEN is low (even parity selected) and there are five high bits on  
the 1A bus, then 1PARITY is set to the logic high level so that an even number of the nine total bits (eight 1A-bus  
bits plus parity bit) are high.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74ABT16657DLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74ABT16657DL TI

完全替代

 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SN74ABT16657DLR TI

完全替代

 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
SN74ABT16657DLG4 TI

类似代替

 16-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS

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