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SN54LV540AJ PDF预览

SN54LV540AJ

更新时间： 2024-09-15 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
7页 132K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LV540AJ 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH DUAL OUTPUT ENABLE系列：LV/LV-A/LVX/H
JESD-30 代码：R-GDIP-T20长度：24.195 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：18.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

SN54LV540AJ 数据手册

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SN54LV540A, SN74LV540A  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS409B – APRIL 1998 – REVISED NOVEMBER 1998  
SN54LV540A . . . J OR W PACKAGE  
SN74LV540A . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
Y1  
Y2  
Y3  
Y4  
A
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Y5  
13 Y6  
12 Y7  
11 Y8  
Package Options Include Plastic  
Small-Outline (DW, NS), Shrink  
GND 10  
Small-Outline (DB), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Flat (W) Packages, Chip  
Carriers (FK), and DIPs (J)  
SN54LV540A . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1 20 19  
18  
Y1  
Y2  
Y3  
Y4  
Y5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
The ’LV540A devices are octal buffers/drivers  
designed for 2-V to 5.5-V V operation.  
17  
16  
15  
14  
CC  
These devices are ideal for driving bus lines or  
buffer memory address registers. They feature  
inputs and outputs on opposite sides of the  
package to facilitate printed circuit board layout.  
9 10 11 12 13  
The 3-state control gate is a two-input AND gate  
with active-low inputs so that if either  
output-enable (OE1 or OE2) input is high, all  
corresponding outputs are in the high-impedance  
state. The outputs provide inverted data when  
they are not in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54LV540A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV540A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer/driver)  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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