SN54LV573

更新时间： 2024-11-05 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
7页	135K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54LV573 数据手册

SN54LV573, SN74LV573

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCLS198B – FEBRUARY 1993 – REVISED APRIL 1996

SN54LV573 . . . J OR W PACKAGE

SN74LV573 . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) 2-µ Process

Typical V

< 0.8 V at V , T = 25°C

(Output Ground Bounce)

OLP

Typical V

> 2 V at V , T = 25°C

(Output V

Undershoot)

OHV

17 3Q

16 4Q

15 5Q

14 6Q

13 7Q

12 8Q

11 LE

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

Latch-Up Performance Exceeds 250 mA

Per JEDEC Standard JESD-17

GND 10

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW),

Ceramic Flat (W) Packages, Chip Carriers

(FK), and (J) 300-mil DIPs

SN54LV573 . . . FK PACKAGE

(TOP VIEW)

description

20 19

These octal transparent D-type latches are

designed for 2.7-V to 5.5-V V operation.

15 5Q

9 10 11 12 13

The ’LV573 feature 3-state outputs designed

specifically for driving highly capacitive or

relatively low-impedance loads. This device is

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The SN74LV573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LV573 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LV573 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN54LV573相关器件

型号	品牌	获取价格	描述	数据表
SN54LV573_10	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573A	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573A_07	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573A_16	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573AFK	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573AJ	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573AW	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573FK	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573J	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LV573W	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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