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SN54LV174AJ PDF预览

SN54LV174AJ

更新时间： 2024-09-15 22:37:11
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
7页 149K
描述
HEX D-TYPE FLIP-FLOPS WITH CLEAR

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SN54LV174AJ 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：CERAMIC, DIP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：LV/LV-A/LVX/HJESD-30 代码：R-GDIP-T16
长度：19.56 mm逻辑集成电路类型：D FLIP-FLOP
位数：6功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：23 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：110 MHzBase Number Matches：1

SN54LV174AJ 数据手册

 浏览型号SN54LV174AJ的Datasheet PDF文件第2页浏览型号SN54LV174AJ的Datasheet PDF文件第3页浏览型号SN54LV174AJ的Datasheet PDF文件第4页浏览型号SN54LV174AJ的Datasheet PDF文件第5页浏览型号SN54LV174AJ的Datasheet PDF文件第6页浏览型号SN54LV174AJ的Datasheet PDF文件第7页 
SN54LV174A, SN74LV174A  
HEX D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS401B – APRIL 1998 – REVISED JULY 1998  
SN54LV174A . . . J OR W PACKAGE  
SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
CC  
A
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
6Q  
6D  
5D  
5Q  
4D  
4Q  
CLK  
OHV  
CC  
OH  
1D  
2D  
A
Latch-Up Performance Exceeds 250 mA  
Per JESD 17  
2Q  
3D  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3Q  
GND  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
SN54LV174A . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18 6D  
1D  
2D  
NC  
2Q  
3D  
4
5
6
7
8
description  
17  
5D  
NC  
5Q  
4D  
16  
15  
14  
The ’LV174A devices are hex D-type flip-flops  
designed for 2-V to 5.5-V V operation.  
CC  
These devices are monolithic positive-edge-  
triggered flip-flops with a direct clear (CLR) input.  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a particular  
voltage level and is not directly related to the  
9 10 11 12 13  
NC – No internal connection  
transition time of the positive-going edge of the clock pulse. When the clock (CLK) input is at either the high or  
low level, the D-input signal has no effect at the output.  
The SN54LV174A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV174A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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