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SN54LV175AW PDF预览

SN54LV175AW

更新时间： 2024-11-24 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
8页 156K
描述
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

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SN54LV175AW 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：LV/LV-A/LVX/H
JESD-30 代码：R-GDFP-F16长度：10.2 mm
逻辑集成电路类型：D FLIP-FLOP位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：27 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：6.73 mm最小 fmax：125 MHz

SN54LV175AW 数据手册

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SN54LV175A, SN74LV175A  
QUADRUPLE D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998  
SN54LV175A . . . J OR W PACKAGE  
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
CLR  
1Q  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
1Q  
1D  
A
Contain Four Flip-Flops With Double-Rail  
Outputs  
2D  
2Q  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
2Q  
GND  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54LV175A . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
2 1 20 19  
18 4Q  
1Q  
1D  
NC  
2D  
2Q  
4
5
6
7
8
Package Options Include Plastic  
17  
4D  
NC  
3D  
3Q  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
16  
15  
14  
9 10 11 12 13  
description  
NC – No internal connection  
The ’LV175A devices are quadruple D-type  
flip-flops designed for 2-V to 5.5-V V operation.  
CC  
These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the  
positive-going edge of the clock (CLK) pulse.  
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the  
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.  
The SN54LV175A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV175A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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