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SN54LS669J PDF预览

SN54LS669J

更新时间: 2024-09-13 23:03:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 216K
描述
SYNCHRONOUS 4-BIT UP/DOWN COUNTER

SN54LS669J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.22其他特性:TCO OUTPUT
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.3 mm负载电容(CL):15 pF
负载/预设输入:YES逻辑集成电路类型:BINARY COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
最大电源电流(ICC):34 mA传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:4.19 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:25 MHzBase Number Matches:1

SN54LS669J 数据手册

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SN54/74LS669  
SYNCHRONOUS 4-BIT  
UP/DOWN COUNTER  
The SN54/74LS669 is a synchronous 4-bit up/down counter. The LS669 is  
a 4-bit binary counter. For high speed counting applications, this presettable  
counter features an internal carry lookahead for cascading purposes. By  
clocking all flip-flops simultaneously so the outputs change coincident with  
each other (when instructed to do so by the count enable inputs and internal  
gating) synchronous operation is provided. This helps to eliminate output  
counting spikes, normally associated with asynchronous (ripple-clock) count-  
ers. Thefourmaster-slaveflip-flopsaretriggeredontherising(positive-going)  
edge of the clock waveform by a buffered clock input.  
SYNCHRONOUS 4-BIT  
UP/DOWN COUNTER  
LOW POWER SCHOTTKY  
Circuitry of the load inputs allows loading with the carry-enable output of the  
cascaded counters. Because loading is synchronous, disabling of the counter  
by setting up a low level on the load input will cause the outputs to agree with  
the data inputs after the next clock pulse.  
J SUFFIX  
CERAMIC  
Cascading counters for N-bit synchronous applications are provided by the  
carry look-ahead circuitry, without additional gating. Two count-enable inputs  
and a carry output help accomplish this function. Count-enable inputs (P and  
T) must both be low to count. The level of the up-down input determines the  
direction of the count. When the input level is low, the counter counts down,  
and when the input is high, the count is up. Input T is fed forward to enable the  
carry output. The carry output will now produce a low level output pulse with a  
CASE 620-09  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
duration equal to the high portion of the Q output when counting up and  
A
1
when counting down equal to the low portion of the Q output. This low level  
A
carry pulse may be utilized to enable successive cascaded stages. Regard-  
less of the level of the clock input, transitions at the P or T inputs are allowed.  
By diode-clamping all inputs, transmission line effects are minimized which  
allows simplification of system design.  
Any changes at control inputs (ENABLE P, ENABLE T, LOAD, UP/DOWN)  
will have no effect on the operating mode until clocking occurs because of the  
fully independant clock circuits. Whether enabled, disabled, loading or count-  
ing, the function of the counter is dictated entirely by the conditions meeting  
the stable setup and hold times.  
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
Programmable Look-Ahead Up/Down Binary/Decade Counters  
Fully Synchronous Operation for Counting and Programming  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Ceramic  
Fully Independent Clock Circuit  
Buffered Outputs  
CONNECTION DIAGRAM (TOP VIEW)  
FAST AND LS TTL DATA  
5-591  

SN54LS669J 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS169N ONSEMI

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BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS

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