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SN54LS16 PDF预览

SN54LS16

更新时间: 2024-09-16 06:12:51
品牌 Logo 应用领域
德州仪器 - TI 驱动器高压
页数 文件大小 规格书
4页 92K
描述
HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUPUTS

SN54LS16 数据手册

 浏览型号SN54LS16的Datasheet PDF文件第2页浏览型号SN54LS16的Datasheet PDF文件第3页浏览型号SN54LS16的Datasheet PDF文件第4页 
SN54LS06, SN54LS16, SN74LS06, SN74LS16  
HEX INVERTER BUFFERS/DRIVERS WITH  
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS  
SDLS020A – MAY 1990  
SN54LS06, SN54LS16 . . . J PACKAGE  
SN74LS06, SN74LS16 . . . D OR N PACKAGE  
Converts TTL Voltage Levels to MOS  
Levels  
(T0P VIEW)  
High Sink-Current Capability  
Input Clamping Diodes Simplify System  
Design  
1A  
1Y  
2A  
2Y  
3A  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
CC  
6A  
6Y  
5A  
5Y  
4A  
4Y  
Open-Collector Driver for Indicator Lamps  
and Relays  
Package Options Include “Small Outline”  
Packages, Ceramic Chip Carriers, and  
Standard Plastic and Ceramic 300-mil DIPs  
3Y  
GND  
8
description  
SN54LS06, SN54LS16 . . . FK PACKAGE  
(T0P VIEW)  
These monolithic hex inverter buffers/drivers  
feature high-voltage open-collector outputs to  
interface with high-level circuits (such as MOS), or  
for driving high-current loads, and are also  
characterized for use as inverter buffers for driving  
TTL inputs. The LS06 has a rated output voltage  
of 30 V and the LS16 has a rated output voltage  
of 15 V. The maximum sink current for the  
SN54LS06 and SN54LS16 is 30 mA and the  
SN74LS06 and SN74LS16 is 40 mA.  
3
2
1
20 19  
18  
6Y  
NC  
5A  
NC  
5Y  
2A  
NC  
2Y  
4
5
6
7
8
17  
16  
15  
14  
NC  
3A  
9 10 11 12 13  
These circuits are compatible with most TTL  
families. Inputs are diode-clamped to minimize  
transmission-effects, which simplifies design.  
Typical power dissipation is 175 mW and average  
propagation delay time is 8 ns.  
NC – No internal connection  
The SN54LS06 and SN54LS16 are characterized over the full military temperature range of 55°C to 125°C.  
The SN74LS06 and SN74LS16 are characterized for operation from 0°C to 70°C.  
logic symbol  
logic diagram (positive logic)  
1
2
4
1A  
2A  
3A  
4A  
5A  
6A  
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
2
1
3
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
1A  
2A  
3A  
4A  
5A  
6A  
3
5
6
4
6
9
8
11  
13  
10  
12  
5
9
8
10  
12  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC  
Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
11  
13  
Copyright 1990, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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