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SN54AS866FK

更新时间： 2024-11-15 19:58:55
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 输出元件逻辑集成电路
页数 文件大小 规格书
7页 126K
描述
Magnitude Comparator, AS Series, 8-Bit, True Output, TTL, CQCC28, CERAMIC, LCC-28

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SN54AS866FK 技术参数

生命周期：Contact Manufacturer包装说明：QCCN,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.72其他特性：OPEN COLLECTOR A = B OUTPUT; ARITHMETIC COMPARISON; CASCADABLE; OUTPUT LATCH
系列：ASJESD-30 代码：S-CQCC-N28
长度：11.43 mm逻辑集成电路类型：MAGNITUDE COMPARATOR
位数：8功能数量：1
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出极性：TRUE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
传播延迟（tpd）：21 ns座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD宽度：11.43 mm
Base Number Matches：1

SN54AS866FK 数据手册

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SDAS183A − DECEMBER 1982 − REVISED JUNE 1990  
SN54AS866 . . . JD PACKAGE  
SN74AS866A . . . N PACKAGE  
(TOP VIEW)  
• Package Options Include Plastic Small  
Outline Packages, Both Plastic and Ceramic  
Chip Carriers, and Standard Plastic and  
Ceramic DIPs  
QLE  
L/A  
V
CC  
1
28  
27  
26  
25  
24  
• Input and Output Latches with Active-High  
CLRQ  
PLE  
P7  
2
Enables  
p < Qin  
P > Qin  
Q7  
3
• Fast Compare to Zero  
4
P6  
5
• Arithmetic and Logical Comparison  
• Open-Collector P = Q Output  
Q6  
6
23 P5  
7
22  
21  
20  
19  
18  
17  
16  
15  
Q5  
P4  
8
Q4  
P3  
description  
9
Q3  
P2  
10  
11  
12  
13  
14  
These Advanced Schottky devices are capable of  
performing high-speed arithmetic or logical  
comparisons on two 8-bit binary or two’s  
complement words. Three fully decoded  
decisions about words P and Q are externally  
available at the outputs. These devices are fully  
expandable to any word length by connecting the  
totem pole P>Q and P<Q outputs of each stage to  
the P>Q and P<Q inputs of the next higher-order  
stage. The cascading paths are implemented with  
only a two-gate-level delay to reduce overall  
comparison times for long words. The open-  
collector P=Q output may be wire-ANDed  
together.  
Q2  
P1  
Q1  
P0  
Q0  
P < Qout  
P > Qout  
OLE  
P = Qout  
GND  
SN54AS866 . . . FK PACKAGE  
SN74AS866A . . . FN PACKAGE  
(TOP VIEW)  
4
3
2 1 28 27 26  
5
6
7
8
9
25 P7  
Q7  
Q6  
Q5  
Q4  
Q3  
Q2  
Q1  
Both input words P and Q plus all three outputs  
(P>Q, P<Q, and P = Q) are equipped with latches  
to provide the designer with temporary data  
storage for avoiding race conditions. The enable  
circuitry is implemented with minimal delay times  
to enhance performance when the devices are  
cascaded for longer word lengths. Each latch is  
transparent when the appropriate latch enable,  
PLE, QLE, or OLE is high.  
24  
23  
22  
21  
20  
19  
P6  
P5  
P4  
P3  
P2  
P1  
10  
11  
12 13 14 15 16 17 18  
The enable inputs PLE and QLE and data inputs  
P and Q utilize pnp input transistors to reduce the  
low-level input current requirement to typically  
−0.25 mA, which minimizes loading effects.  
The Q register may be cleared to zero for a fast comparison of the P word to zero.  
The SN54AS866 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74AS866A is characterized for operation from 0°C to 70°C.  
Copyright 1990, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1234567

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