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SN54AS869JT PDF预览

SN54AS869JT

更新时间： 2024-09-30 22:20:03
品牌 Logo 应用领域
德州仪器 - TI 计数器
页数 文件大小 规格书
17页 288K
描述
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS

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SN54AS869JT 技术参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.53其他特性：TCO OUTPUT; COUNT ENABLE INPUTS
计数方向：BIDIRECTIONAL系列：AS
JESD-30 代码：R-GDIP-T24JESD-609代码：e0
长度：32.005 mm负载电容（CL）：50 pF
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：40000000 Hz
最大I（ol）：0.02 A工作模式：SYNCHRONOUS
位数：8功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：195 mA
Prop。Delay @ Nom-Sup：35 ns传播延迟（tpd）：16 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Counters最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：40 MHz

SN54AS869JT 数据手册

 浏览型号SN54AS869JT的Datasheet PDF文件第2页浏览型号SN54AS869JT的Datasheet PDF文件第3页浏览型号SN54AS869JT的Datasheet PDF文件第4页浏览型号SN54AS869JT的Datasheet PDF文件第5页浏览型号SN54AS869JT的Datasheet PDF文件第6页浏览型号SN54AS869JT的Datasheet PDF文件第7页 
SN54AS867, SN54AS869  
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869  
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS  
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995  
SN54AS867, SN54AS869 . . . JT PACKAGE  
• Fully Programmable With Synchronous  
SN74ALS867A, SN74ALS869, SN74AS867,  
SN74AS869 . . . DW OR NT PACKAGE  
(TOP VIEW)  
Counting and Loading  
• SN74ALS867A and ′AS867 Have  
Asynchronous Clear; SN74ALS869 and  
′AS869 Have Synchronous Clear  
S0  
S1  
A
B
C
D
E
F
G
V
CC  
ENP  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
• Fully Independent Clock Circuit  
Q
3
Simplifies Use  
A
Q
B
4
• Ripple-Carry Output for n-Bit Cascading  
Q
5
C
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic  
(NT) and Ceramic (JT) 300-mil DIPs  
Q
D
6
Q
7
E
Q
F
8
Q
9
G
H
ENT  
GND  
Q
H
CLK  
10  
11  
12  
description  
RCO  
These synchronous, presettable, 8-bit up/down  
counters feature internal-carry look-ahead  
circuitry for cascading in high-speed counting  
applications. Synchronous operation is provided  
by having all flip-flops clocked simultaneously so  
that the outputs change coincidentally with each  
other when so instructed by the count-enable  
(ENP, ENT) inputs and internal gating. This mode  
of operation eliminates the output counting spikes  
normally associated with asynchronous (ripple-  
clock) counters. A buffered clock (CLK) input  
triggers the eight flip-flops on the rising (positive-  
going) edge of the clock waveform.  
SN54AS867, SN54AS869 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1 28 27 26  
25  
B
C
Q
Q
Q
5
B
C
D
24  
23  
22  
21  
20  
19  
6
D
7
NC  
E
NC  
8
Q
9
E
F
10  
11  
Q
Q
F
These counters are fully programmable; they may  
be preset to any number between 0 and 255. The  
load-input circuitry allows parallel loading of the  
cascaded counters. Because loading is  
synchronous, selecting the load mode disables  
the counter and causes the outputs to agree with  
the data inputs after the next clock pulse.  
G
G
12 13 14 15 16 17 18  
NC – No internal connection  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. Two count-enable (ENP and ENT) inputs and a ripple-carry (RCO) output are instrumental  
in accomplishing this function. Both ENP and ENT must be low to count. The direction of the count is determined  
by the levels of the select (S0, S1) inputs as shown in the function table. ENT is fed forward to enable RCO. RCO  
thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting  
up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages.  
Transitions at ENP and ENT are allowed regardless of the level of CLK. All inputs are diode clamped to minimize  
transmission-line effects, thereby simplifying system design.  
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the  
SN74ALS867A and ′AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q  
outputs until clocking occurs. For the ′AS867 and ′AS869, any time ENP and/or ENT is taken high, RCO either  
goes or remains high. For the SN74ALS867A and SN74ALS869, any time ENT is taken high, RCO either goes  
or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely  
by the conditions meeting the stable setup and hold times.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

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SN54AS869JT 替代型号

型号 品牌 替代类型 描述 数据表
5962-8966801LA TI

完全替代

 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
5962-8952601LA TI

完全替代

 SYNCHRONOUS 8-BIT UP/DOWN COUNTERS

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SN54AS86AJ TI

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 		QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN54AS86FK TI

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 		AS SERIES, QUAD 2-INPUT XOR GATE, CQCC20
SN54AS873A TI

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 		DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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 		DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54AS873AJT TI

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 		DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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 		IC AS SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CQCC28, CERAMIC, LCC-28, Bus Driver/Transcei
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