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SN54AS873JT PDF预览

SN54AS873JT

更新时间: 2024-11-15 21:18:39
品牌 Logo 应用领域
德州仪器 - TI 驱动逻辑集成电路
页数 文件大小 规格书
8页 119K
描述
Dual 4-Bit D-type Latches With 3-State Outputs 24-CDIP -55 to 125

SN54AS873JT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP24,.3针数:24
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.56其他特性:WITH CLEAR
系列:ASJESD-30 代码:R-GDIP-T24
长度:32.005 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.032 A
位数:4功能数量:2
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):110 mA
Prop。Delay @ Nom-Sup:14 ns传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN54AS873JT 数据手册

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SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A  
DUAL 4-BIT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SDAS036D – APRIL 1982 – REVISED AUGUST 1995  
SN54ALS873B, SN54AS873A . . . JT PACKAGE  
SN74ALS873B, SN74AS873A . . . DW OR NT PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
1CLR  
1OE  
1D1  
1D2  
1D3  
1D4  
2D1  
2D2  
2D3  
V
CC  
1
2
3
4
5
6
7
8
9
24  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
23 1LE  
22 1Q1  
21 1Q2  
20 1Q3  
19 1Q4  
18 2Q1  
17 2Q2  
16 2Q3  
15 2Q4  
14 2LE  
13 2CLR  
description  
These dual 4-bit D-type latches feature 3-state  
outputs designed specifically for bus driving.  
These devices are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
2D4 10  
2OE 11  
GND 12  
The dual 4-bit latches are transparent D-type  
latches. While the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs in true  
form, according to the function table. When LE is  
low, the outputs are latched. When the clear (CLR)  
SN54ALS873B, SN54AS873A . . . FK PACKAGE  
(TOP VIEW)  
input goes low, the  
Q
outputs go low  
independently of LE. The outputs are in the  
high-impedance state when the output-enable  
(OE) input is at a high logic level.  
4
3
2
1 28 27 26  
25  
1D2  
1D3  
1D4  
NC  
2D1  
2D2  
2D3  
1Q2  
1Q3  
1Q4  
NC  
2Q1  
2Q2  
2Q3  
5
6
7
8
9
24  
23  
22  
21  
20  
19  
The SN54ALS873B and SN54AS873A are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS873B  
and  
SN74AS873A  
are  
10  
11  
characterized for operation from 0°C to 70°C.  
12 13 14 15 16 17 18  
NC – No internal connection  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
X
D
X
H
L
CLR  
L
L
H
L
L
H
H
H
L
L
H
L
H
X
X
Q
0
H
X
X
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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