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SN54ALS561A

更新时间： 2024-11-05 23:06:11

品牌	Logo	应用领域
德州仪器 - TI		计数器输出元件
页数	文件大小	规格书
9页	156K
描述
SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS

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SN54ALS561A 数据手册

SN54ALS561A, SN74ALS561A

SYNCHRONOUS 4-BIT COUNTERS

WITH 3-STATE OUTPUTS

SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995

SN54ALS561A . . . J PACKAGE

SN74ALS561A . . . DW OR N PACKAGE

(TOP VIEW)

• Carry Output for n-Bit Cascading

• Buffer-Type Outputs Drive Bus Lines

Directly

• Choice of Asynchronous or Synchronous

ALOAD

CLK

Clearing and Loading

RCO

CCO

• Internal Look-Ahead Circuitry for Fast

Cascading

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic (N)

and Ceramic (J) 300-mil DIPs

ENP

ACLR

SCLR

GND

ENT

SLOAD

description

These binary counters are programmable and

offer synchronous and asynchronous clearing as

well as synchronous and asynchronous loading.

All synchronous functions are executed on the

positive-going edge of the clock.

SN54ALS561A . . . FK PACKAGE

(TOP VIEW)

The clear function is initiated by applying a low

level to either asynchronous clear (ACLR) or

synchronous clear (SCLR). ACLR (direct clear)

overrides all other functions of the device, while

SCLR overrides only the other synchronous

functions. Data is loaded from the A, B, C, and D

inputs by applying a low level to asynchronous

load (ALOAD) or by the combination of a low level

20 19

CCO

ENP

ACLR

9 10 11 12 13

at synchronous load (SLOAD) and

positive-going clock transition. The counting

function is enabled only when enable P (ENP),

enable T (ENT), ACLR, ALOAD, SCLR, and

SLOAD are all high.

A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level

enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output

(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces

a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is

enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated

with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter

to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because

CCO does not become active until the clock returns to the low level.

The SN54ALS561A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ALS561A is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

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与SN54ALS561A相关器件

型号	品牌	获取价格	描述	数据表
SN54ALS561A_11	TI	获取价格	SYNCHRONOUS 4-BIT COUNTERS
SN54ALS561AFH	ROCHESTER	获取价格	Binary Counter,
SN54ALS561AFH-00	TI	获取价格	ALS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CQCC20
SN54ALS561AFK	TI	获取价格	SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS
SN54ALS561AJ	TI	获取价格	SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS
SN54ALS561AJ-00	TI	获取价格	ALS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP20
SN54ALS561FH	ROCHESTER	获取价格	Binary Counter,
SN54ALS561J	TI	获取价格	IC,COUNTER,UP,4-BIT BINARY,ALS-TTL,DIP,20PIN,CERAMIC
SN54ALS563A	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ALS563AFK	TI	获取价格	OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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