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SN54ALS561AFK PDF预览

SN54ALS561AFK

更新时间： 2024-11-05 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 计数器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
9页 156K
描述
SYNCHRONOUS 4-BIT COUNTERS WITH 3-STATE OUTPUTS

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SN54ALS561AFK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：CERAMIC, CC-20
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.78
Is Samacsys：N其他特性：TCO OUTPUT; COUNT ENABLE INPUTS
计数方向：UP系列：ALS
JESD-30 代码：S-CQCC-N20长度：8.89 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER工作模式：SYNCHRONOUS
位数：4功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装等效代码：LCC20,.35SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：33 mA
传播延迟（tpd）：21 ns认证状态：Not Qualified
座面最大高度：2.03 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：8.89 mm
最小 fmax：25 MHzBase Number Matches：1

SN54ALS561AFK 数据手册

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SN54ALS561A, SN74ALS561A  
SYNCHRONOUS 4-BIT COUNTERS  
WITH 3-STATE OUTPUTS  
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995  
SN54ALS561A . . . J PACKAGE  
SN74ALS561A . . . DW OR N PACKAGE  
(TOP VIEW)  
• Carry Output for n-Bit Cascading  
• Buffer-Type Outputs Drive Bus Lines  
Directly  
• Choice of Asynchronous or Synchronous  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
ALOAD  
CLK  
A
V
CC  
Clearing and Loading  
RCO  
CCO  
OE  
• Internal Look-Ahead Circuitry for Fast  
B
C
D
Cascading  
Q
Q
Q
Q
A
B
C
D
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
ENP  
ACLR  
SCLR  
GND  
ENT  
SLOAD  
description  
These binary counters are programmable and  
offer synchronous and asynchronous clearing as  
well as synchronous and asynchronous loading.  
All synchronous functions are executed on the  
positive-going edge of the clock.  
SN54ALS561A . . . FK PACKAGE  
(TOP VIEW)  
The clear function is initiated by applying a low  
level to either asynchronous clear (ACLR) or  
synchronous clear (SCLR). ACLR (direct clear)  
overrides all other functions of the device, while  
SCLR overrides only the other synchronous  
functions. Data is loaded from the A, B, C, and D  
inputs by applying a low level to asynchronous  
load (ALOAD) or by the combination of a low level  
3
2
1
20 19  
18  
4
5
6
7
8
B
C
CCO  
OE  
17  
16  
15  
14  
D
Q
Q
Q
A
B
C
ENP  
ACLR  
9 10 11 12 13  
at synchronous load (SLOAD) and  
a
positive-going clock transition. The counting  
function is enabled only when enable P (ENP),  
enable T (ENT), ACLR, ALOAD, SCLR, and  
SLOAD are all high.  
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level  
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output  
(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces  
a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is  
enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated  
with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter  
to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because  
CCO does not become active until the clock returns to the low level.  
The SN54ALS561A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS561A is characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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