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SN54ALS569A_08

更新时间: 2024-11-23 05:18:19
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德州仪器 - TI 计数器输出元件
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描述
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS WITH 3-STATE OUTPUTS

SN54ALS569A_08 数据手册

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SN54ALS569A, SN74ALS568A, SN74ALS569A  
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS  
WITH 3-STATE OUTPUTS  
SDAS229A – APRIL 1982 – REVISED JANUARY 1995  
SN54ALS569A . . . J PACKAGE  
SN74ALS568A, SN74ALS569A . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Q Outputs Drive Bus Lines Directly  
Counter Operation Independent of 3-State  
Output  
Fully Synchronous Clear, Count, and Load  
Asynchronous Clear Is Also Provided  
Fully Cascadable  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) 300-mil DIPs  
U/D  
CLK  
A
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
RCO  
CCO  
OE  
B
C
D
Q
A
Q
B
ENP  
ACLR  
SCLR  
GND  
Q
C
Q
D
12 ENT  
description  
11  
LOAD  
The SN74ALS568A decade counter and  
ALS569A binary counters are programmable,  
count up or down, and offer both synchronous and  
asynchronous clearing. All synchronous functions  
are executed on the positive-going edge of the  
clock (CLK) input.  
SN54ALS569A . . . FK PACKAGE  
(TOP VIEW)  
The clear function is initiated by applying a low  
level to either asynchronous clear (ACLR) or  
synchronousclear(SCLR). Asynchronous(direct)  
clearing overrides all other functions of the device,  
while synchronous clearing overrides only the  
other synchronous functions. Data is loaded from  
the A, B, C, and D inputs by holding load (LOAD)  
low during a positive-going clock transition. The  
counting function is enabled only when enable P  
(ENP) and enable T (ENT) are low and ACLR,  
SCLR, and LOAD are high. The up/down (U/D)  
input controls the direction of the count. These  
counters count up when U/D is high and count  
down when U/D is low.  
3
2
1
20 19  
18  
CCO  
OE  
B
C
4
5
6
7
8
17  
16  
15  
14  
Q
D
A
Q
B
ENP  
ACLR  
Q
C
9 10 11 12 13  
A high level at the output-enable (OE) input forces the Q outputs into the high-impedance state, and a low level  
enables those outputs. Counting is independent of OE. ENT is fed forward to enable the ripple-carry output  
(RCO) to produce a low-level pulse while the count is zero (all Q outputs low) when counting down or maximum  
(9 or 15) when counting up. The clocked carry output (CCO) produces a low-level pulse for a duration equal to  
that of the low level of the clock when RCO is low and the counter is enabled (both ENP and ENT are low);  
otherwise, CCO is high. CCO does not have the glitches commonly associated with a ripple-carry output.  
Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter.  
However, for very high-speed counting, RCO should be used for cascading since CCO does not become active  
until the clock returns to the low level.  
The SN54ALS569A is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74ALS568A and SN74ALS569A are characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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